Programmable control block for dual port SRAM application
View Patent ↗A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle.
1. A method of operating a circuit, the method comprising:
determining a target phase shift between a first clock signal and a second clock signal;
delaying the second clock signal relative to the first clock signal based on the target phase shift; and
triggering a memory access operation using the first clock signal and the second clock signal.
2. The method of claim 1 , wherein the determining comprises setting the target phase shift to a value greater than specified lower bound and less than a specified upper bound.
3. The method of claim 1 , wherein the delaying comprises setting at least one value of at least one programmable delay chain.
4. The method of claim 3 , wherein setting the at least one value of the at least one programmable delay chain comprises:
setting a value of a first programmable delay chain, the first programmable delay chain controlling a fine delay amount; and
setting a value of a second programmable delay chain, the second programmable delay chain controlling a coarse delay amount.
5. The method of claim 1 , wherein the memory access operation is a read-then-write operation.
6. The method of claim 1 , wherein the circuit is an FPGA.
7. The method of claim 1 , wherein the circuit is a static random access memory.
8. An integrated circuit comprising:
delay circuitry configured to:
determine a target phase shift between a first clock signal and a second clock signal; and
delay the second clock signal relative to the first clock signal based on the target phase shift; and
control circuitry configured to initiate a memory access operation using the first clock signal and the second clock signal.
9. The integrated circuit of claim 8 , wherein the delay circuitry is further configured to set the target phase shift to a value greater than specified lower bound and less than a specified upper bound.
10. The integrated circuit of claim 8 , wherein the delay circuitry is further configured to delay the second clock signal by setting at least one parameter of a programmable delay chain.
11. The integrated circuit of claim 10 , wherein the delay circuitry is further configured to set the at least one parameter of the programmable delay chain by:
setting a first parameter of the programmable delay chain based on a target fine delay amount; and
setting a second parameter of the programmable delay chain based on a target coarse delay amount.
12. The integrated circuit of claim 8 , wherein the memory access operation is a read-then-write operation.
13. The integrated circuit of claim 8 , wherein the integrated circuit is an FPGA.
14. The integrated circuit of claim 8 , wherein the integrated circuit is a static random access memory.
15. An integrated circuit comprising:
delay circuitry configured to delay a first clock signal relative to a second clock signal based on a target phase shift; and
control circuitry configured to perform a memory access operation based on the first clock signal and the second clock signal.
16. The integrated circuit of claim 15 , wherein the delay circuitry is further configured to set the target phase shift to a value greater than specified lower bound and less than a specified upper bound.
17. The integrated circuit of claim 15 , wherein the delay circuitry is further configured to set the delay using a first delay element, to set a fine adjustment to the delay, and a second delay element, to set a coarse adjustment to the delay.
18. The integrated circuit of claim 15 , wherein the memory access operation is a read-then-write operation.
19. The integrated circuit of claim 15 , wherein the integrated circuit is an FPGA.
20. The integrated circuit of claim 15 , wherein the integrated circuit is a static random access memory.