FACE-TO-FACE THROUGH-SILICON VIA MULTI-CHIP SEMICONDUCTOR APPARATUS WITH REDISTRIBUTION LAYER PACKAGING AND METHODS OF ASSEMBLING SAME
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
1 . A multi-die apparatus, comprising:
a first semiconductive device having a first side and a second side, the first side above the second side, and the first side having metallization, the first semiconductive device further comprising a plurality of through silicon vias extending from the metallization to the second side;
a first bump in contact with the metallization of the first side of the first semiconductive device;
a second bump in contact with the metallization of the first side of the first semiconductive device;
a second semiconductive device having a first side and a second side, the second side above the first side, and the first side having metallization, the metallization coupled to the first bump;
a third semiconductive device having a first side and a second side, the second side above the first side, and the first side having metallization, the metallization coupled to the second bump; and
a redistribution layer on the second side of the first semiconductive device, the redistribution layer having a via in direct physical contact with one of the plurality of through silicon vias of the first semiconductive device, and the redistribution layer having a trace that contacts the via.
2 . The multi-die apparatus of claim 1 , wherein the via is an inner via.
3 . The multi-die apparatus of claim 2 , further comprising:
one or more outer vias below the trace.
4 . The multi-die apparatus of claim 1 , wherein the second semiconductive device and the third semiconductive device have a same thickness.
5 . The multi-die apparatus of claim 1 , wherein the second semiconductive device and the third semiconductive device have different thicknesses.
6 . The multi-die apparatus of claim 1 , wherein the second semiconductive device is entirely within a footprint of the first semiconductive device.
7 . The multi-die apparatus of claim 6 , wherein the third semiconductive device is entirely within a footprint of the first semiconductive device.
8 . A multi-die apparatus, comprising:
a first device having an active side opposite a backside, the active side having metallization, the first device further comprising a through silicon via extending from the metallization to the backside;
a first bump in contact with the metallization of the active side of the first device;
a second bump in contact with the metallization of the active side of the first device;
a second device above the first device, the second device having an active side opposite a backside, the active side having metallization facing the first device, the metallization coupled to the first bump;
a third device above the first device, the third device having an active side opposite a backside, the active side having metallization facing the first device, the metallization coupled to the second bump;
a via below and in direct physical contact with the through silicon via of the first device; and
a trace below and in contact with the via.
9 . The multi-die apparatus of claim 8 , wherein the via is an inner via, the multi-die apparatus of claim, further comprising:
an outer via below the trace.
10 . The multi-die apparatus of claim 8 , wherein the second device and the third device have a same thickness.
11 . The multi-die apparatus of claim 8 , wherein the second device and the third device have different thicknesses.
12 . The multi-die apparatus of claim 8 , wherein the second device is entirely within a footprint of the first device.
13 . The multi-die apparatus of claim 12 , wherein the third device is entirely within a footprint of the first device.
14 . A method of fabricating a multi-die apparatus, the method comprising:
forming a first semiconductive device having a first side and a second side, the first side above the second side, and the first side having metallization, the first semiconductive device further comprising a plurality of through silicon vias extending from the metallization to the second side;
forming a first bump in contact with the metallization of the first side of the first semiconductive device;
forming a second bump in contact with the metallization of the first side of the first semiconductive device;
coupling a second semiconductive device to the first semiconductive device, the second semiconductive device having a first side and a second side, the second side above the first side, and the first side having metallization, the metallization coupled to the first bump;
coupling a third semiconductive device to the first semiconductive device, the third semiconductive device having a first side and a second side, the second side above the first side, and the first side having metallization, the metallization coupled to the second bump; and
forming a redistribution layer on the second side of the first semiconductive device, the redistribution layer having a via in direct physical contact with one of the plurality of through silicon vias of the first semiconductive device, and the redistribution layer having a trace that contacts the via.
15 . The method of claim 14 , wherein the via is an inner via.
16 . The method of claim 15 , further comprising:
forming one or more outer vias below the trace.
17 . The method of claim 14 , wherein the second semiconductive device and the third semiconductive device have a same thickness.
18 . The method of claim 14 , wherein the second semiconductive device and the third semiconductive device have different thicknesses.
19 . The method of claim 14 , wherein the second semiconductive device is entirely within a footprint of the first semiconductive device.
20 . The method of claim 19 , wherein the third semiconductive device is entirely within a footprint of the first semiconductive device.