Systems and methods for preventing data remanence in memory systems
Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.
1. A circuit comprising:
a first memory comprising:
a data input;
a data output signal; and
a complemented data output signal;
a second memory comprising:
a data input;
a data output signal; and
a complemented data output signal; and
exclusive-OR circuitry that provides a circuit output signal as a logical exclusive-OR function of the data output signal of the first memory and the data output signal of the second memory;
selection circuitry that uses a load signal to select between an input signal to the circuit or the complemented data output signal of the first memory as a selection circuit output signal, wherein the second memory is reset in response to the load signal; and
interconnection circuitry that couples the complemented data output signal of the second memory to the data input of the second memory.
2. The circuit of claim 1 , comprising a clock that drives the first memory and the second memory.
3. The circuit of claim 2 , wherein the second memory alternates between a logical high and a logical low on successive clock pulses from the clock.
4. The circuit of claim 2 , wherein the second memory receives the load signal at a reset port of the second memory to reset an output of the second memory upon assertion of the load signal.
5. The circuit of claim 1 , wherein the interconnection circuitry couples the load signal to a reset port of the second memory that resets the data output signal of the second memory to a reset value.
6. The circuit of claim 1 , wherein the interconnection circuitry couples the selection circuit output signal to data input of the first memory.
7. The circuit of claim 1 , wherein the load signal is received from outside the circuit.
8. The circuit of claim 5 , comprising level shifter circuitry to couple the load signal with selection circuitry and the second memory by translating voltage levels.
9. The circuit of claim 1 , wherein selection circuitry comprises a multiplexer that receives the input signal to the circuit and the complemented data output signal that outputs:
when the load signal is not asserted, the complemented data output signal of the first memory; and
when the load signal is asserted, the input signal to the circuit.
10. The circuit of claim 1 , comprising level shifter circuitry to couple the input signal to the circuit with the selection circuitry by translating voltage levels.
11. The circuit of claim 1 , wherein the first memory comprises a plurality of single bit data registers, and the second memory comprises only one single bit data register.
12. The circuit of claim 1 , wherein the first memory comprises randomly accessible memory.
13. The circuit of claim 12 , wherein the first memory comprises static random access memory (SRAM) or dynamic random access memory (DRAM).
14. The circuit of claim 1 , wherein the input signal to the circuit comprises a cryptographic key.
15. A circuit comprising:
a first memory comprising:
a data input;
a data output signal; and
a complemented data output signal;
a second memory comprising:
a data input;
a data output signal; and
a complemented data output signal; and
exclusive-OR circuitry that provides a circuit output signal as a logical exclusive-OR function of the data output signal of the first memory and the data output signal of the second memory;
selection circuitry that uses a load signal to select between an input signal to the circuit or the complemented data output signal of the first memory as a selection circuit output signal, wherein the second memory is reset in response to the load signal and the selection circuitry loads the input signal to the circuit into the first memory in response to the load signal; and
interconnection circuitry that:
couples the complemented data output signal of the second memory to the data input of the second memory;
couples the load signal to a reset of the second memory that resets the data output signal of the second memory to a reset value; and
couple the selection circuit output signal to data input of the first memory.
16. The circuit of claim 15 , wherein the second memory includes less bits than the first memory, the second memory periodically inverts the data output signal of the second memory based on a clock signal, and periodic inversion of the second memory reduces occurrences of data remanence in the circuit output signal.
17. The circuit of claim 16 , wherein the load signal is coupled to a reset port of the second memory to reset the second memory to a known state.
18. The circuit of claim 15 , wherein the first memory comprises static random access memory (SRAM) or dynamic random access memory (DRAM).
19. A field-programmable gate array (FPGA) comprising:
a first memory comprising:
a data input;
a data output signal; and
a complemented data output signal;
a second memory comprising:
a data input;
a data output signal;
a reset port that resets in response to a load signal; and
a complemented data output signal; and
exclusive-OR circuitry that provides a circuit output signal as a logical exclusive-OR function of the data output signal of the first memory and the data output signal of the second memory;
selection circuitry that uses the load signal to select between an input signal to the FPGA or the complemented data output signal of the first memory as a selection circuit output signal, wherein the second memory is reset in response to the load signal; and
interconnection circuitry that couples the complemented data output signal of the second memory to the data input of the second memory.
20. The FPGA of claim 19 , wherein the second memory includes less bits than the first memory, the second memory periodically inverts the data output signal of the second memory based on a clock signal, and periodic inversion of the second memory reduces occurrences of data remanence in the circuit output signal.