Implementation of related clocks
View Patent ↗An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.
1. An integrated circuit (IC) comprising:
a plurality of configurable circuits for performing a plurality of operations, each operation defined by one of a plurality of different sets of configuration data; and
a reconfiguration counter for providing a reconfiguration state to the configurable circuits, the reconfiguration state for selecting a set of the configuration data from the plurality of sets of configuration data, wherein the reconfiguration counter advances count to a next reconfiguration state when it receives a count enable signal, wherein the count enable signal is modulated so the configurable circuits perform the plurality of operations at a user specified data rate.
2. The IC of claim 1 , wherein the user specified data rate correspond to a user defined clock.
3. The IC of claim 2 , wherein the plurality of operations is performed as part of a user design, where the user design is specified by using the user defined clock.
4. The IC of claim 2 , wherein the plurality of operations is for performing user defined operations that are defined by referencing the user defined clock.
5. The IC of claim 2 , wherein the reconfiguration counter operates on a base clock that is faster than the user defined clock.
6. The IC of claim 1 , wherein the count of the reconfiguration counter returns to an initial count when the reconfiguration state reaches a final reconfiguration state.
7. The IC of claim 1 , wherein the reconfiguration state loopers to an initial reconfiguration state after reaching a terminal count.
8. An integrated circuit (IC) comprising:
a first set of reconfigurable circuits for implementing a first clock domain of a user design, wherein the first set of reconfigurable circuits has a first reconfiguration state that loopers at a first rate; and
a second set of reconfigurable circuits for implementing a second clock domain of the user design, wherein the second set of reconfigurable circuits has a second reconfiguration state that loopers at a second rate that is different from the first rate, wherein a particular reconfigurable circuit in the second set of reconfigurable circuits synchronously receives a signal from the first set of reconfigurable circuit.
9. The IC of claim 8 , wherein the loopering of the first reconfiguration state is controlled by a first modulated count enable signal to a first reconfiguration counter that provides the first reconfiguration state.
10. The IC of claim 9 , wherein the loopering of the second reconfiguration state is controlled by a second modulated count enable signal that is modulated differently from the first modulated count enable signal.
11. The IC of claim 8 , wherein the loopering of the first reconfiguration state comprises a first number of reconfiguration states and the loopering of the second reconfiguration state comprises a second number of reconfiguration states, wherein the first number of reconfiguration states is different from the second number of reconfiguration states.
12. The IC of claim 8 , wherein the loopering of the first reconfiguration state comprises a first number of reconfiguration states and the loopering of the second reconfiguration state comprises a second number of reconfiguration states, wherein the first number of reconfiguration states is the same as the second number of reconfiguration states.
13. The IC of claim 8 , wherein the first reconfiguration state advances K states in L clock cycles, wherein the second reconfiguration state advances M states in N clock cycles, wherein K, L, M, and N are integers.
14. The IC of claim 13 , wherein N is different than L.
15. The IC of claim 13 , wherein M is different than K.
16. The IC of claim 8 , wherein the synchronously received signal is statically scheduled in the user design.
17. An integrated circuit (IC) for implementing a user design, the user design comprising:
a first clock domain operating at a first user clock;
a second clock domain operating at a second user clock that is different from the first user clock; and
a signal that travels from the first clock domain to a second clock domain at a time slot that is statically scheduled.
18. The IC of claim 17 , wherein the IC comprises a first set of reconfigurable circuits for implementing the first clock domain and a second set of reconfigurable circuits for implementing the second clock domain.
19. The IC of claim 18 , wherein the first set of reconfigurable circuits is controlled by a first reconfiguration signal and the second set of reconfigurable circuits is controlled by a second reconfiguration signal.
20. The IC of claim 19 , wherein the first reconfiguration signal completes one looper in one cycle of the first user clock and the second reconfiguration signal completes one looper in one cycle of the second user clock.
21. The IC of claim 19 , wherein the statically scheduled time slot occurs when the first reconfiguration signal is at a first reconfiguration state and the second reconfiguration is at a second reconfigurable state.