Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices
View Patent ↗In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.
1. Multiplier circuitry comprising:
partial products generation circuitry;
partial products addition circuitry; and
routing circuitry for selectively routing to the partial products addition circuitry either (a) partial products output by the partial products generation circuitry or (b) data previously output by the partial products addition circuitry and data that has not passed through the partial products generation circuitry.
2. The circuitry defined in claim 1 further comprising:
incrementer circuitry for selectively incrementing data previously output by the incrementer circuitry with a signal that has not passed through the partial products generation circuitry or the partial products addition circuitry.
3. The circuitry defined in claim 1 further comprising:
input register circuitry for outputting signals to the partial products generation circuitry and the routing circuitry.
4. The circuitry defined in claim 3 further comprising:
input interface circuitry; and
multiplexer circuitry for selectively applying to the input register circuitry either (a) signals from the input interface circuitry or (b) signals output by the partial products addition circuitry of another instance of multiplier circuitry that is substantially the same as the multiplier circuitry.
5. The circuitry defined in claim 1 further comprising:
output register circuitry that is capable of storing output signals of the partial products addition circuitry.
6. The circuitry defined in claim 5 wherein the data previously output by the partial products addition circuitry is derived from the output register circuitry.
7. The circuitry defined in claim 1 wherein the partial products addition circuitry includes an output lead for conveying an overflow output signal of the partial products addition circuitry.
8. The circuitry defined in claim 7 further comprising:
incrementer circuitry for selectively incrementing data previously output by the incrementer circuitry with the overflow output signal from another instance of multiplier circuitry that is substantially the same as the multiplier circuitry.
9. The circuitry defined in claim 8 further comprising:
output register circuitry; and
second routing circuitry for selectively applying to the output register circuitry either (a) output signals of the partial products addition circuitry or (b) output signals of the incrementer circuitry.
10. The circuitry defined in claim 9 wherein the data previously output by the incrementer circuitry is derived from the output register circuitry.
11. A programmable logic device comprising multiplier circuitry as defined in claim 1 .
12. A digital processing system comprising:
processing circuitry;
a memory coupled to said processing circuitry; and
a programmably logic device as defined in claim 11 coupled to the processing circuitry and the memory.
13. A printed circuit board on which is mounted a programmable logic device as defined in claim 11 .
14. The printed circuit board defined in claim 13 further comprising:
a memory mounted on the printed circuit board and coupled to the programmable logic device.
15. The printed circuit board defined in claim 13 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
16. Digital signal processing circuitry comprising:
a plurality of multiplier blocks, each including partial products generation circuitry, partial products addition circuitry, output register circuitry, and multiplexer circuitry for selectively applying to the partial products addition circuitry either (a) partial products output by the partial products generation circuitry or (b) signals fed back from the output register circuitry and signals that have not passed through the partial products generation circuitry; and
interconnection circuitry for applying output signals of the partial products addition circuitry in a first of the multiplier blocks to the multiplexer circuitry in a second of the multiplier blocks as the signals that have not passed through the partial products generation circuitry of the second multiplier block.
17. The circuitry defined in claim 16 wherein each of the multiplier blocks further includes incrementer circuitry for selectively incrementing signals fed back from the output register circuitry with a signal from another one of the multiplier blocks.
18. The circuitry defined in claim 17 wherein the signal from another one of the multiplier blocks comprises an overflow output signal of the partial products addition circuitry in the another one of the multiplier blocks.
19. The circuitry defined in claim 17 wherein each of the multiplier blocks still further includes second multiplexer circuitry for selectively applying to the output register circuitry either (a) output signals of the partial products addition circuitry or (b) output signals of the incrementer circuitry.
20. The circuitry defined in claim 19 wherein the second multiplexer circuitry is programmably controlled.
21. The circuitry defined in claim 16 wherein each of the multiplier blocks further includes input register circuitry, output signals of which are applied to the partial products generation circuitry and the multiplexer circuitry as the signals that have not passed through the partial products generation circuitry.
22. The circuitry defined in claim 21 wherein each of the multiplier blocks further includes input interface circuitry and second multiplexer circuitry for selectively applying to the input register circuitry either (a) outputs of the input interface circuitry or (b) signals from the interconnection circuitry.
23. The circuitry defined in claim 22 wherein the second multiplexer circuitry is programmably controlled.
24. The circuitry defined in claim 16 wherein the multiplexer circuitry is programmably controlled.
25. A method of operating DSP circuitry that includes a plurality of multiplier blocks, each having partial products generation circuitry, partial products addition circuitry for adding partial products output by the partial products generation circuitry in a multiply mode of operation, and output register circuitry for registering output signals of the partial products addition circuitry in the multiply mode of operation, the method comprising:
selectively using the partial products addition circuitry in a first of the multiplier blocks to add the output signals of the partial products addition circuitry in a second of the multiplier blocks and output signals of the output register circuitry in the first of the multiplier blocks.
26. The method defined in claim 25 wherein each of the multiplier blocks further includes incrementer circuitry, and wherein the method further comprises:
selectively using the incrementer circuitry in the second multiplier block to accumulate any overflow from the partial products addition circuitry in the first multiplier block.