Apparatus and methods for high-speed interpolator-based clock and data recovery

1. A clock and data recovery circuit comprising:

a sampler circuit arranged to receive a data signal and a sampling clock and generate a feedback signal which is responsive to a phase of the data signal relative to the sampling clock signal;

a de-multiplexer circuit arranged to de-multiplex the feedback signal and output a de-multiplexed feedback signal;

a voting circuit arranged to decimate the de-multiplexed feedback signal and output a decimated feedback signal comprising preliminary up and down signals;

a digital filter circuit arranged to filter the decimated feedback signal from the voting circuit and to output a filtered feedback signal comprising up and down signals which are filtered versions of the preliminary up and down signals;

a finite state machine circuit arranged to receive the filtered feedback signal and generate an interpolator control signal; and

a phase interpolator circuit arranged to generate the sampling clock responsive to a reference clock and the interpolator control signal.

2. The clock and data recovery circuit of claim 1 , wherein the de-multiplexer circuit comprises higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.

3. The clock and data recovery circuit of claim 2 , wherein the sampler and the phase interpolator circuits operate at a higher speed while the voting and finite state machine circuits operate at a slower speed.

4. The clock and data recovery circuit of claim 1 , wherein the feedback signal comprises an early signal indicating that the sampling clock is leading the data signal and a late signal indicating that the sampling clock is lagging the data signal.

5. The clock and data recovery circuit of claim 4 , wherein the de-multiplexer circuit includes a first sub-circuit to de-multiplex the early signal and a second sub-circuit to de-multiplex the late signal.

6. The clock and data recovery circuit of claim 1 , wherein the de-multiplexer circuit is programmable to a plurality of de-multiplexing settings.

7. The clock and data recovery circuit of claim 6 , wherein the voting circuit comprises a majority voting circuit with a plurality of programmable settings for at least one of the de-multiplexer settings.

8. The clock and data recovery circuit of claim 1 , wherein the digital filter is programmable to a plurality of filter settings.

9. A method for clock and data recovery from a data signal, the method comprising:

generating a feedback signal which is responsive to a phase of a data signal relative to a sampling clock signal;

de-multiplexing the feedback signal to generate a de-multiplexed feedback signal;

decimating the de-multiplexed feedback signal to generate a decimated feedback signal comprising preliminary up and down signals;

filtering the decimated feedback signal to generate a filtered feedback signal comprising up and down signals which are filtered versions of the preliminary up and down signals;

generating an interpolator control signal using the filtered feedback signal and a finite state machine; and

generating the sampling clock by interpolation using a reference clock and the interpolator control signal.

10. The method of claim 9 , wherein the de-multiplexing is performed by higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.

11. The method of claim 10 , wherein the feedback signal and the sampling clock are generated by circuitry operating at a higher speed, while the decimated feedback signal, the filtered feedback signal, and interpolator control signal are generated by circuitry operating at a lower speed.

12. The method of claim 9 , wherein the feedback signal comprises an early signal indicating that the sampling clock is leading the data signal and a late signal indicating that the sampling clock is lagging the data signal.

13. The method of claim 12 , wherein the early and late signals are each de-multiplexed by a 1:N de-multiplexer, wherein N is programmable to one of a plurality of numbers.

14. The method of claim 13 , wherein the decimating is performed by a majority voting circuit which is programmable to one of a plurality of settings.

15. The method of claim 14 , wherein the filtering is performed by a digital filter circuit which is programmable to one of a plurality of settings.

16. A receiver for a data link, the receiver comprising:

a buffer circuit arranged to receive a data signal and generate a buffered data signal; and

a programmable clock and data recovery circuit arranged to generate a sampling clock from the buffered data signal, the clock and data recovery circuit including

a sampler arranged to generate a feedback signal which is responsive to a phase of the data signal relative to the sampling clock signal,

a programmable de-multiplexer arranged to de-multiplex the feedback signal and output a de-multiplexed feedback signal,

a programmable voting circuit arranged to decimate the de-multiplexed feedback signal and output a decimated feedback signal comprising preliminary up and down signals,

a digital filter arranged to filter the decimated feedback signal and output a filtered feedback signal comprising up and down signals which are filtered versions of the preliminary up and down signals,

a finite state machine arranged to receive the filtered feedback signal and generate an interpolator control signal, and

a phase interpolator arranged to generate the sampling clock responsive to a reference clock and the interpolator control signal.

17. The receiver of claim 16 , wherein the programmable de-multiplexer is configurable to a plurality of de-multiplexer settings.

18. The receiver of claim 17 , wherein the voting circuit comprises a majority voting circuit with a plurality of programmable settings for at least one of the de-multiplexer settings.

19. The receiver of claim 16 , wherein the programmable de-multiplexer comprises higher-speed circuit blocks which are arranged to receive the feedback signal and lower-speed circuit blocks which are arranged to output the de-multiplexed feedback signal.

20. The receiver circuit of claim 19 , wherein the sampler and the phase interpolator operate at a higher speed while the voting circuit, digital filter, and finite state machine operate at a slower speed.