Reduced matrix Reed-Solomon encoding
View Patent ↗In an arrangement of the disclosed systems, devices, and methods, a matrix representation of a block code comprising m bit-planes is obtained, a generator matrix corresponding to each of the m bit-planes from the matrix representation is extracted, a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code are determined, a reverse-mapped transformed generator matrix for each of the second bit-plane through the m th bit-plane of the block code are determined, and instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the m th bit-plane of the block code are generated.
1. Circuitry for producing a plurality of check symbols comprising:
input circuitry configured to receive a data vector comprising a plurality of data symbols, each data symbol having a bit-depth m;
a plurality of adder banks comprising:
a first adder bank configured to process the data vector to produce a transformed data vector by appending a plurality of parameters to the data vector;
a plurality of m additional adder banks, each configured to process a respective bit-slice of the transformed data vector to produce an output based on a respective reverse-mapped generator matrix; and
a reducer bank configured to process the outputs of each of the plurality of m additional adder banks to produce the plurality of check symbols.
2. The circuitry of claim 1 , wherein each reverse-mapped generator matrix is produced based on the transformed data vector.
3. The circuitry of claim 1 , further comprising:
a plurality of m sets of data connections corresponding, respectively, to inputs to the plurality of m additional adder banks.
4. The circuitry of claim 1 , wherein the plurality of parameters is generated according to an iterative matrix transform.
5. The circuitry of claim 3 , wherein the set of data connections corresponding to a given adder bank in the plurality of m additional adder banks is based on the non-zero entries of a corresponding reverse-mapped generator matrix.
6. A method for configuring an encoder architecture comprising:
obtaining a matrix representation of a block code comprising m bit-planes;
extracting a generator matrix corresponding to each of the m bit-planes from the matrix representation;
determining a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code;
determining a reverse-mapped transformed generator matrix for each of the second bit-plane through the m th bit-plane of the block code; and
generating instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the m th bit-plane of the block code.
7. The method of claim 6 , wherein determining the reverse-mapped transformed generator matrix for a bit-plane of the block code is based on the transformed data symbol vector.
8. The method of claim 6 , further comprising extracting a data symbol vector from the first plane of the block code.
9. The method of claim 6 , wherein determining the reverse-mapped transformed generator matrix for a bit-plane of the block code comprises generating a frequency match matrix based on the transformed generator matrix for the first bit-plane.
10. The method of claim 6 , wherein the instructions are in the form of a configuration layout file.
11. The circuitry of claim 6 , wherein the block code is a (n, k, m) Reed-Solomon code.
12. The circuitry of claim 6 , wherein the instructions for the encoder architecture are for implementation in an Field Programmable Gate Array (FPGA).
13. The method of claim 9 , wherein determining the reverse-mapped transformed generator matrix for the bit-plane of the block code further comprises adding a column to the reverse-mapped transformed generator matrix in response to a determination that a highest frequency element of the frequency match matrix is greater than a predefined value.
14. Circuitry for producing a plurality of check symbols comprising:
input circuitry configured to receive a data vector comprising a plurality of data symbols, each data symbol having a bit-depth m;
for each of m bit-slices of a block code,
a first adder bank configured to process the data vector to produce a transformed data vector based on the respective bit-slice; and
a second adder bank configured to process the transformed data vector based on a reverse-mapped generator matrix for the bit-slice to produce an output; and
a reducer bank configured to process the output of each second adder bank corresponding to each of the m bit-slices of the block code to produce the plurality of check symbols.
15. The circuitry of claim 14 , wherein the first adder bank is further configured to produce the transformed data vector by appending a plurality of parameters to the data vector.
16. The circuitry of claim 14 , wherein each reverse-mapped generator matrix is produced based on the transformed data vector.
17. The circuitry of claim 16 , wherein the plurality of parameters is generated according to an iterative matrix transform.
18. The circuitry of claim 14 , wherein the block code is a (n, k, m) Reed-Solomon code.
19. The circuitry of claim 14 , wherein the circuitry is implemented in an Field Programmable Gate Array (FPGA).