Techniques for reducing skew between clock signals

1. A circuit comprising:

a clock signal generation circuit to generate a first clock signal based on second and third clock signals, wherein the clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals; and

a skew reduction circuit to reduce skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin of the clock signal generation circuit.

2. The circuit of claim 1 , wherein the skew reduction circuit comprises a time-to-digital converter circuit to measure the skew between the second and the third clock signals.

3. The circuit of claim 2 , wherein the time-to-digital converter circuit comprises:

a coarse skew time-to-digital converter circuit to measure a coarse skew between the second and the third clock signals; and

a fine skew time-to-digital converter circuit to measure a fine skew between the second and the third clock signals.

4. The circuit of claim 1 , wherein the skew reduction circuit comprises a detector circuit to generate a directional signal indicating whether a phase of the second clock signal is leading or lagging a phase of the third clock signal.

5. The circuit of claim 4 , wherein the skew reduction circuit further comprises:

a first delay line to provide a coarse delay to the second clock signal in response to a coarse skew measured between the second and the third clock signals if the directional signal indicates that the phase of the second clock signal is leading the phase of the third clock signal; and

a second delay line to provide a fine delay to the second clock signal in response to a fine skew measured between the second and the third clock signals if the directional signal indicates that the phase of the second clock signal is leading the phase of the third clock signal, wherein the coarse delay is larger than the fine delay.

6. The circuit of claim 5 , wherein the skew reduction circuit further comprises:

a third delay line to provide the coarse delay to the third clock signal in response to the coarse skew measured between the second and the third clock signals if the directional signal indicates that the phase of the third clock signal is leading the phase of the second clock signal; and

a fourth delay line to provide the fine delay to the third clock signal in response to the fine skew measured between the second and the third clock signals if the directional signal indicates that the phase of the third clock signal is leading the phase of the second clock signal.

7. The circuit of claim 1 , wherein the skew reduction circuit comprises a first delay circuit to generate the second clock signal based on the first clock signal and a second delay circuit to generate the third clock signal based on a fourth clock signal, wherein the skew reduction circuit generates a measurement of the skew between the second and the third clock signals, and wherein the skew reduction circuit adjusts a delay of at least one of the first and the second delay circuits to reduce the skew between the second and the third clock signals based on the measurement of the skew.

8. The circuit of claim 1 , wherein the clock signal generation circuit comprises a detector circuit to generate a phase error signal that indicates the phase difference between the second and the third clock signals, wherein the skew reduction circuit reduces the skew between the second and the third clock signals in response to the phase error signal, and wherein the clock signal generation circuit comprises at least one of a phase-locked loop circuit or a delay-locked loop circuit.

9. The circuit of claim 1 , wherein the clock signal generation circuit comprises a lock detector circuit that generates a lock signal to indicate when the second and the third clock signals are aligned in phase within a static phase offset, and wherein the skew reduction circuit reduces the skew between the second and the third clock signals in response to the lock signal.

10. A circuit comprising:

a clock signal generation circuit to generate a first clock signal based on second and third clock signals, wherein the clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals; and

a skew reduction circuit to generate an indication of a skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin, wherein the skew reduction circuit reduces the skew between the second and the third clock signals based on the indication of the skew between the second and the third clock signals.

11. The circuit of claim 10 , wherein the skew reduction circuit generates the second clock signal based on the first clock signal.

12. The circuit of claim 10 , wherein the skew reduction circuit comprises:

a coarse skew time-to-digital converter circuit to measure a coarse skew between the second and the third clock signals; and

a fine skew time-to-digital converter circuit to measure a fine skew between the second and the third clock signals, wherein the skew reduction circuit reduces the coarse skew and the fine skew measured between the second and the third clock signals.

13. The circuit of claim 10 , wherein the skew reduction circuit comprises a detector circuit to generate a directional signal indicating whether a phase of the second clock signal is leading or lagging a phase of the third clock signal, and wherein the skew reduction circuit determines whether to adjust a delay provided to the second clock signal or to adjust a delay provided to the third clock signal to reduce the skew based on the directional signal.

14. The circuit of claim 10 , wherein the skew reduction circuit comprises:

first delay circuits coupled in a first delay line to provide a coarse delay to the second clock signal in response to an indication of a coarse skew between the second and the third clock signals if the second clock signal is leading the third clock signal; and

second delay circuits coupled in a second delay line to provide a fine delay to the second clock signal in response to an indication of a fine skew between the second and the third clock signals if the second clock signal is leading the third clock signal, wherein the coarse delay is larger than the fine delay.

15. The circuit of claim 14 , wherein the skew reduction circuit further comprises:

third delay circuits coupled in a third delay line to provide the coarse delay to the third clock signal in response to the indication of the coarse skew between the second and the third clock signals if the third clock signal is leading the second clock signal; and

fourth delay circuits coupled in a fourth delay line to provide the fine delay to the third clock signal in response to the indication of the fine skew between the second and the third clock signals if the third clock signal is leading the second clock signal.

16. The circuit of claim 10 , wherein the skew reduction circuit comprises a controller circuit to control a measurement of a coarse skew between the second and the third clock signals and to control a measurement of a fine skew between the second and the third clock signals, and wherein the skew reduction circuit removes the coarse and the fine skews measured between the second and the third clock signals.

17. A method comprising:

generating a first clock signal based on second and third clock signals using a clock signal generation circuit;

generating an indication of a phase difference between the second and the third clock signals using the clock signal generation circuit;

generating an indication of a skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin using a skew reduction circuit; and

reducing the skew between the second and the third clock signals based on the indication of the skew between the second and the third clock signals using the skew reduction circuit.

18. The method of claim 17 , wherein generating an indication of a skew between the second and the third clock signals comprises measuring the skew between the second and the third clock signals using a time-to-digital converter circuit.

19. The method of claim 17 , wherein reducing the skew between the second and the third clock signals comprises:

generating the second clock signal based on the first clock signal using a first delay circuit;

generating the third clock signal based on a fourth clock signal using a second delay circuit; and

adjusting a delay of at least one of the first and the second delay circuits to reduce the skew between the second and the third clock signals based on the indication of the skew between the second and the third clock signals.

20. The method of claim 17 , wherein generating an indication of a skew between the second and the third clock signals comprises:

generating a directional signal using a storage circuit that indicates whether a phase of the second clock signal is leading or lagging a phase of the third clock signal; and

adjusting a delay provided to one of the second clock signal or the third clock signal to reduce the skew between the second and the third clock signals based on the directional signal using the skew reduction circuit.