Method and apparatus for automatic hierarchical design partitioning
View Patent ↗A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.
1. A method for synthesis of a circuit in a target integrated circuit (IC) device that comprises programmable logic, wherein the programmable logic comprises a set of logic sections, each logic section associated with a physical location, wherein the method comprises:
receiving a circuit design for the target IC device, wherein the circuit design comprises at least one constraint for the target IC device;
dividing automatically the circuit design into a set of partitions, wherein the division balances an assignment of resources of the target IC device to produce a partitioned circuit design, and wherein each partition is associated with a physical location of a respective logic section of the set of logic sections;
generating a bit stream based on the target IC device and the partitioned circuit design; and
programming the target IC device using the bit stream.
2. The method of claim 1 , wherein dividing automatically the circuit design into the set of partitions is based on the at least one constraint for the circuit.
3. The method of claim 1 , wherein the partitioned circuit design comprises a plurality of cross-boundary couplings, and wherein dividing automatically the circuit design comprises using a cost function that comprises cross-boundary optimizations.
4. The method of claim 1 , wherein the target IC device comprises interconnect lines that couple at least two partitions of the set of partitions.
5. The method of claim 1 , wherein dividing the circuit design comprises timing criticality information.
6. A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause the processor to:
receive a circuit design for a target integrated circuit (IC) device, wherein the circuit design comprises at least one constraint for the target IC device;
produce a partitioned circuit design comprising a plurality of partitions based on resources of the target IC device, wherein each partition is associated with a respective physical location of the target IC device; and
program the target IC device using a bit stream generated from the partitioned circuit design.
7. The non-transitory computer readable medium of claim 6 , wherein producing the partitioned circuit design comprises using a cost function that comprises the at least one constraint for the circuit design.
8. The non-transitory computer readable medium of claim 6 , wherein the target IC device comprises a plurality of cross-boundary couplings.
9. The non-transitory computer readable medium of claim 8 , wherein at least one cross-boundary coupling comprises an interconnect line that couples two partitions of the plurality of partitions.
10. The non-transitory computer readable medium of claim 8 , wherein producing the partitioned circuit design comprises minimizing a number of cross-boundary couplings in the plurality of cross-boundary couplings.
11. The non-transitory computer readable medium of claim 6 , wherein producing the partitioned circuit design is based on timing criticality information.
12. The non-transitory computer readable medium of claim 6 , wherein producing the partitioned circuit design is based on a count of resources.
13. A system comprising an integrated circuit (IC) device that comprises programmable logic circuitry programmed with a bit stream, wherein the programmable logic circuitry comprises a plurality of logic sections and wherein the bit stream was generated by a method that comprises:
receiving a circuit design for the programmable logic circuitry, wherein the circuit design comprises at least one constraint for the IC device;
generating the plurality of logic sections based on resources of the IC device, wherein each logic section comprises a portion of the circuit design;
generating a partitioned circuit design by assigning each logic section of the plurality of logic sections to a respective physical location of the IC device;
generating the bit stream based on the partitioned circuit design; and
programming the programmable logic circuitry with the bit stream.
14. The system of claim 13 , wherein generating the plurality of logic sections is based on a cost function that comprises the at least one constraint for the circuit design.
15. The system of claim 13 , comprising a plurality of cross-boundary couplings, and wherein generating the plurality of logic sections comprises identifying at least one cross-boundary coupling of the plurality of cross-boundary couplings.
16. The system of claim 15 , wherein at least one cross-boundary coupling comprises an interconnect line that couples two partitions of the plurality of logic sections.
17. The system of claim 15 , wherein producing the partitioned circuit design comprises minimizing a number of cross-boundary couplings in the plurality of cross-boundary couplings.
18. The system of claim 13 , wherein the partitioned circuit design comprises timing criticality information.
19. The system of claim 13 , wherein the generating the plurality of logic sections comprises identifying a count of resources.
20. The system of claim 13 , comprising a processor coupled to the IC device.
21. The system of claim 20 , comprising a printed circuit board that is coupled to the processor and the IC device.
22. The system of claim 13 , wherein the IC device comprises a structured applicant-specific integrated circuit that comprises processing circuitry.
23. The system of claim 13 , comprising a memory coupled to the IC device.