Method and apparatus for generating systolic arrays on a target device using a high-level synthesis language

1. A method for generating a description of a systolic array, comprising:

prompting a user to input information about the systolic array to be implemented on a target device; and

generating a high-level synthesis language that describes channels of processing elements of the systolic array and a topology of the processing elements from the information provided by the user; and

reducing clock latency for the processing elements by creating a zero-depth FIFO for each non-diagonal processor element connection.

2. The method of claim 1 , wherein the high-level synthesis language further describes data transmitters and data receivers associated with the systolic array.

3. The method of claim 1 , wherein the high-level synthesis language further describes an external interface associated with the systolic array.

4. The method of claim 1 , wherein the high-level synthesis language further describes components in the processing elements of the systolic array.

5. The method of claim 1 further comprising performing optimizations on the high-level synthesis language.

6. The method of claim 5 , wherein performing optimizations on the high-level synthesis language comprises performing external channel fan-out minimization.

7. The method of claim 5 , wherein performing optimizations on the high-level synthesis language comprises performing data buffering in the processing elements.

8. The method of claim 5 , wherein performing optimizations on the high-level synthesis language comprises reducing clock latency for the processing elements.

9. The method of claim 1 , wherein prompting the user to provide information about the systolic array comprises prompting the user to provide a functional description of the processing elements and a dimension of the processing elements in a computer language format.

10. The method of claim 1 , wherein the high-level synthesis language is OpenCL.

11. The method of claim 1 , wherein generating the description of the channels of processing elements is performed in response to a functional description of the processing elements provided by the user.

12. The method of claim 1 , wherein generating the topology of the processing elements is performed in response to a dimension of the systolic array provided by the user.

13. The method of claim 1 further comprising generating a description of components in the processing elements in the systolic array in response to an algorithmic description of the processing elements provided by the user.

14. A method for generating a description of a systolic array in a high-level synthesis language, comprising:

generating a description of a typology of the systolic array to be implemented on a target device in response to a dimension of the systolic array;

generating a description of components in processing elements in the systolic array in response to an algorithmic description of the processing elements; and

generating a description of channels between the processing elements in response to a functional description of the processing elements; and

reducing clock latency for the processing elements by creating a zero-depth FIFO for each non-diagonal processor element connection.

15. The method of claim 14 further comprising optimizing the systolic array by performing external channel fan-out minimization.

16. The method of claim 14 further comprising adding data buffers in the processing elements.

17. The method of claim 14 , wherein the high-level synthesis language is OpenCL.

18. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method, comprising:

prompting a user to input information about a systolic array to be implemented on a target device; and

generating a high-level synthesis language that describes a typology of the systolic array and components in processing elements of the systolic array in response to the information provided by the user; and

modifying the high-level synthesis language by performing parallelism expansion, external channel fan-out minimization, data buffering, and latency reduction.

19. The non-transitory computer readable medium of claim 18 , wherein generating the high-level synthesis language comprises:

generating a description of the typology of the systolic array in response to a dimension of the systolic array; and

generating a description of the components in the processing elements in the systolic array in response to an algorithmic description of the processing elements.

20. The non-transitory computer-readable medium of claim 19 , wherein the method further comprises converting the high-level synthesis language to hardware description language.

21. The non-transitory computer-readable medium of claim 19 , wherein the converting comprises converting kernel functions in the high-level synthesis language to hardware components to implement the kernel functions in the hardware description language.

22. The non-transitory computer readable medium of claim 18 , wherein the method further comprises generating a description of channels between the processing elements in response to a functional description of the processing elements.

23. The non-transitory computer readable medium of claim 18 , wherein the method further comprises performing optimizations on the high-level synthesis language that describes the systolic array.

24. The non-transitory computer readable medium of claim 18 , wherein the high-level synthesis language is OpenCL.

25. A system designer, comprising:

a high-level synthesis language unit that generates a high-level synthesis language that describes a typology of a systolic array to be implemented on a target device and components in processing elements of the systolic array in response to information provided by the user; and

an optimization unit that modifies the high-level synthesis language to improve throughput and performance, wherein the optimization unit modifies the high-level synthesis language by performing parallelism expansion, external channel fan-out minimization, data buffering, and latency reduction.