IP Library Granted Patent US 10,361,708
Granted Patent B1
US 10,361,708 · App. 15/277,783 · Granted Jul 23, 2019

Systems and methods for sharing multiple lock-detect circuitries or multiple phase locked loop blocks

Inventors: Christopher Thomas Moore (Saratoga, CA); Bo Zhou (Milpitas, CA); Rajiv Kane (Fremont, CA)
Assignee: ALTERA CORPORATION
H03L7/095H03L7/0807H03L7/099H03L7/23H04L7/0331
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Quick Facts
Patent No.
US 10,361,708
App. No.
15/277,783
Granted
Jul 23, 2019
Kind
B1
Abstract

Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.

Claims (19)

1. An electrical system comprising:

a phase-locked loop circuitry comprising an internal lock-detect circuitry, wherein the phase-locked loop circuitry produces an output clock signal and the internal lock-detect circuitry produces a first lock-detect signal, wherein the internal lock-detect comprises an analog lock-detect circuitry;

an external lock-detect circuitry external to the phase-locked loop circuitry that receives at least a return clock signal from the phase-locked loop circuitry and provides a second lock-detect signal, wherein the external lock-detect circuitry comprises a digital lock-detect circuitry; and

a selector module that receives the first lock-detect signal and the second lock-detect signal and provides an output lock-detect signal that indicates a quality of the output clock signal.

2. The electrical system of claim 1 , wherein the external lock-detect circuitry has a first error range substantially smaller than a second error range of the internal lock-detect circuitry.

3. The electrical system of claim 1 , wherein the quality of the output clock signal comprises a difference between a reference clock signal and the return clock signal.

4. The electrical system of claim 1 , wherein the external lock-detect circuitry has an error range of less than a part per million.

5. The electrical system of claim 1 , wherein the phase-locked loop circuitry includes an integer multiplier.

6. The electrical system of claim 1 , wherein the phase-locked loop circuitry includes a fractional multiplier.

7. The electrical system of claim 1 , comprising a second phase-locked loop circuitry comprising a second internal lock-detect circuitry, wherein the second phase-locked loop circuitry produces a second output clock signal and the external lock-detect circuitry receives at least the second output clock signal from the second phase-locked loop circuitry and provides the second lock-detect signal that indicates a quality of the second output clock signal.

8. The electrical system of claim 1 , wherein the external lock-detect circuitry receives a reference clock signal and the return clock signal from the phase-locked loop circuitry and produces a lock-detect signal based on the reference clock signal and the return clock signal.

9. An electrical system comprising:

a phase-locked loop circuitry that produces an output clock signal based on a reference clock signal;

a first lock-detect circuitry that receives at least the reference clock signal and a return clock signal and produces a first lock-detect signal that indicates a quality of the output clocks signal within a first error range; and

a second lock-detect circuitry that receives at least the reference clock signal and the return clock signal and produces a second lock-detect signal that indicates the quality of the output clock signal within a second error range substantially smaller than the first error range.

10. The electrical system of claim 9 , wherein the phase-locked loop circuitry comprises a selector module receives the first lock-detect signal and the second lock-detect signal and produces a third lock-detect signal.

11. The electrical system of claim 10 , wherein the selector module provides the first lock-detect signal as the third lock-detect signal and a reduces a power of the second lock-detect circuitry is reduced.

12. The electrical system of claim 9 , wherein the reference clock signal comprises a serial data signal.

13. The electrical system of claim 9 , wherein the first lock-detect circuitry is an analog lock-detect circuitry and the second lock-detect circuitry is a digital lock-detect circuitry.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2016
From: MOORE, CHRISTOPHER THOMAS; ZHOU, BO; KANE, RAJIV
To: ALTERA CORPORATION
Reel/Frame 040152/0938 →