IP Library Granted Patent US 10,417,169
Granted Patent B1
US 10,417,169 · App. 15/264,293 · Granted Sep 17, 2019

Methods and apparatus for high-speed serial interface link assist

Inventors: Han Hua Leong (Butterworth, MY); Suresh Gordhanlal Andani (Fremont, CA); Peter Schepers (Bornem, BE)
Assignee: Altera Corporation
G06F13/4286G06F11/076G06F11/0745G06F11/0793G06F13/102G06F13/20
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Quick Facts
Patent No.
US 10,417,169
App. No.
15/264,293
Granted
Sep 17, 2019
Kind
B1
Abstract

The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for serial interface link assist. Another embodiment relates to a method of dynamic reconfiguration of transceiver settings. Another embodiment relates to a method of tuning a bidirectional serial link. Other features, aspects and embodiments are also disclosed.

Claims (33)

1. A method of managing transceiver settings for a target transceiver in a target device, the method comprising:

entering a link assist mode by a link assist controller of the target transceiver such that the link assist controller is a slave to a master controller of a partner transceiver;

receiving commands from the master controller by the link assist controller;

using the commands to reconfigure the transceiver settings of the target transceiver; and

exiting the link assist mode by the link assist controller such that the target transceiver enters a normal operating mode.

2. The method of claim 1 , wherein slots in a handshaking frame are used to communicate the commands and status data between the link assist controller and the master controller to perform the reconfiguration of the target transceiver.

3. The method of claim 1 , further comprising:

using a memory-mapped interface decoder to access and reconfigure dynamic partial reconfiguration input-output blocks and soft configuration and status registers on the target device.

4. The method of claim 1 , further comprising:

using a memory-mapped interface decoder to connect to a reconfiguration network.

5. The method of claim 4 , wherein the reconfiguration network provides access to a design compilation tool.

6. The method of claim 1 further comprising tuning a bidirectional serial link between the target transceiver in the target device and the partner transceiver in a partner device by:

entering the link assist mode by the link assist controller of the target transceiver such that the link assist controller is a slave to the master controller of the partner transceiver; and

separately testing both directions of the link and also testing a round-trip path over the link.

7. The method of claim 6 , wherein the target transceiver comprises a target transmitter and a target receiver, and the partner transceiver comprises a partner transmitter and a partner receiver, the method further comprising:

sending commands from the master controller to the link assist controller to cause the target transmitter to send a first test pattern to the partner receiver;

determining a first bit error rate by comparing data received by the partner receiver against the first test pattern; and

adjusting settings for the partner receiver and/or the target transmitter if the first bit error rate is not zero.

8. The method of claim 7 , further comprising:

sending a second test pattern from the partner transmitter to the target receiver;

determining a second bit error rate by comparing data received by the target receiver against the second test pattern; and

adjusting settings for the target receiver and/or the partner transmitter if the second bit error rate is not zero.

9. The method of claim 8 , further comprising:

sending commands from the master controller to the link assist controller to configure the target transceiver in loopback mode;

sending a third test pattern in a loop from the partner transmitter to the target receiver to the target transmitter to the partner receiver;

determining a third bit error rate by comparing data received by the partner receiver against the third test pattern.

10. The method of claim 9 , further comprising:

exiting the link assist mode by the target transceiver if the third bit error rate is below a target bit error rate.

11. The method of claim 6 , wherein the master controller comprises the link assist controller in the partner transceiver.

12. The method of claim 6 , wherein the master controller is implemented in a software stack for the partner transceiver.

13. The method of claim 6 , wherein entering the link assist mode is effectuated in response to performing handshaking between the master controller of the partner transceiver and the link assist controller of the target transceiver.

14. The method of claim 1 , wherein entering the link assist mode is effectuated in response to performing handshaking between the master controller of the partner transceiver and the link assist controller of the target transceiver.

15. The method of claim 1 further comprising sending the commands from the master controller to the link assist controller to reconfigure the transceiver settings of the target transceiver.

Assignments (1)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
Continuity (1)
Continuation 14982664 · Dec 29, 2015