Systems and methods for detecting and mitigating programmable logic device tampering
View Patent ↗Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
1. A programmable integrated circuit device comprising:
a register for storing a dirty bit; and
a control block for:
determining whether the dirty bit is set before beginning a configuration attempt,
setting the dirty bit and beginning the configuration attempt in response to determining that the dirty bit is not set, and
clearing the dirty bit after successfully configuring programmable integrated circuit device, and
initiating an anti-tampering operation in response to determining that the dirty bit is set.
2. The programmable integrated circuit device of claim 1 , wherein the control block is further configured to issue an alarm in response to determining that the dirty bit is set before beginning the configuration attempt.
3. The programmable integrated circuit device of claim 1 , wherein the control block is further configured to:
modify an error counter value in response to determining that the dirty bit is set before beginning the configuration attempt, and wherein the anti-tampering operation occurs if the error counter value equals a first threshold value and if the dirty bit is set.
4. The programmable integrated circuit device of claim 3 , wherein the anti-tampering operation is a first anti-tampering operation, and wherein the control block is further configured to initiate a second anti-tampering operation when the error counter value equals a second threshold value, wherein the first threshold value is different from the second threshold value.
5. The programmable integrated circuit device of claim 1 , wherein the first anti-tampering operation includes at least one of clearing a key stored in the programmable integrated circuit device and killing the programmable integrated circuit device.
6. A method of mitigating tampering of a programmable integrated circuit device comprising:
determining, using a control block, whether a dirty bit is set before beginning a configuration attempt;
setting the dirty bit and beginning the configuration attempt in response to determining that the dirty bit is not set; and
clearing the dirty bit after successfully configuring programmable integrated circuit device;
initiating, using a control block, an anti-tampering operation in response to determining that the dirty bit is set.
7. The method of claim 6 further comprising issuing an alarm in response to determining that the dirty bit is set before beginning the configuration attempt.
8. The method of claim 6 further comprising:
modifying an error counter value in response to determining that the dirty bit is set before beginning the configuration attempt, wherein the anti-tampering operation occurs if the error counter value equals a first threshold value and if the dirty bit is set.
9. The method of claim 8 , wherein the anti-tampering operation is a first anti-tampering operation, further comprising initiating a second anti-tampering operation when the error counter value equals a second threshold value, wherein the first threshold value is different from the second threshold value.
10. The method of claim 6 , wherein the first anti-tampering operation includes at least one of clearing a key stored in the programmable integrated circuit device and killing the programmable integrated circuit device.
11. A programmable integrated circuit device comprising:
a register that is configured to store a value of an error counter; and
a control block that is configured to:
configure the programmable integrated circuit device,
modify the value of the error counter in response to an unsuccessful configuration attempt,
determine whether the value of the error counter equals a first threshold, and
initiate a first anti-tampering operation in response to the value of the error counter equaling the first threshold.
12. The programmable integrated circuit device of claim 11 further comprising logic circuitry configured to reset the value of the error counter after a configuration attempt completes successfully.
13. The programmable integrated circuit device of claim 11 , wherein the control block is further configured to determine whether the value of the error counter equals a second threshold.
14. The programmable integrated circuit device of claim 13 , wherein the control block is further configured to initiate a second anti-tampering operation when the value of the error counter is determined to equal the second threshold, wherein the first anti-tampering operation and the second anti-tampering operation are different.
15. The programmable integrated circuit device of claim 11 , wherein modifying the value of the error counter includes at least one of incrementing and decrementing the value of the error counter.
16. A method of mitigating tampering of a programmable integrated circuit device comprising:
receiving an initiation signal to configure the programmable integrated circuit device;
modifying a value of an error counter in response to an unsuccessful attempt to configure the programmable integrated circuit device if the value of the error counter has been previously set;
determining whether the value of the error counter equals a first threshold; and
initiating, using a control block, a first anti-tampering operation in response to the value of the error counter equaling the first threshold.
17. The method of claim 16 further comprising resetting the value of the error counter after a configuration attempt completes successfully.
18. The method of claim 16 further comprising determining whether the value of the error counter equals a second threshold.
19. The method of claim 18 further comprising initiating a second anti-tampering operation when the value of the error counter is determined to equal the second threshold, wherein the first anti-tampering operation and the second anti-tampering operation are different.
20. The method of claim 16 , wherein modifying the value of the error counter includes at least one of incrementing and decrementing the value of the error counter.