Integrated circuit with tamper-detection and self-erase mechanisms
Methods and apparatuses for improving security of an integrated circuit (IC) are provided. A tamper condition is detected and a digital key stored in the IC is erased. The digital key is associated with a first image loaded onto the IC from a first memory. The memory may be a non-volatile memory module. A second image is loaded into a second memory module. The second memory module may be an embedded memory module, e.g., a control random access memory (CRAM) module. The first image is then erased from the first and second memory modules.
1. A method of improving security of an integrated circuit (IC), the method comprising:
detecting a tamper condition;
erasing a digital key stored in the IC, wherein the digital key is associated with a first configuration data loaded onto the IC from a first memory, wherein the first memory is external to the IC; and
loading a second configuration data from the first memory into a second memory in response to detecting the tamper condition, wherein the second memory is external to the first memory and internal to the IC, and
erasing the first configuration data from the first memory, wherein the loading of the second configuration data occurs prior to the erasing the first configuration data from the first memory, wherein the second configuration data configures the IC to transmit an erase signal to erase the first configuration data stored in the first memory, and wherein each method operation is controlled by internal circuitry within the IC.
2. The method of claim 1 further comprising:
transitioning to a reconfiguration mode prior to the loading of the second configuration data.
3. The method of claim 1 , wherein the first configuration data is an encrypted configuration bitstream, and wherein the second configuration data is an unencrypted configuration bitstream.
4. The method of claim 1 , wherein the loading of the second configuration data replaces the first configuration data, wherein the first configuration data is configuration data destined for a static random access memory (SRAM) module in the IC.
5. The method of claim 1 , further comprising:
disabling a scan chain interface in the IC based on the tamper condition.
6. The method of claim 1 , further comprising:
verifying the erasing of the digital key through a scan chain interface on the IC.
7. A method of operating an integrated circuit (IC), the method comprising:
loading a configuration file into a control random access memory (CRAM) on the IC in a first operating mode, wherein the configuration file is loaded from an external memory module coupled to the IC;
in a second operating mode, receiving a tamper-detect signal;
placing the IC in the first operating mode;
loading a predetermined configuration from the external memory module onto the CRAM in response to the receiving, wherein the predetermined configuration replaces the configuration file in the CRAM; and
transmitting a signal for erasing the configuration file from the external memory module, wherein the predetermined configuration configures the IC to perform the transmitting the signal for erasing the configuration file from the external memory module.
8. The method of claim 7 , wherein the configuration file stored in the external memory module is an encrypted file and wherein the predetermined configuration is an unencrypted file.
9. The method of claim 7 further comprising:
erasing a security key that enables access to the configuration file from the IC prior to the loading the predetermined configuration.
10. The method of claim 7 , wherein the loading the predetermined configuration onto the CRAM and transmitting the signal are controlled by a core logic block on the IC.
11. The method of claim 7 further comprising:
disabling external access to a scan chain interface of the IC prior to the erasing of the configuration file from the CRAM.
12. The method of claim 7 further comprising:
clocking the loading the predetermined configuration and the transmitting the signal for erasing the configuration file from the external memory module with an internal clock source of the IC.
13. The method of claim 7 , wherein the first operating mode is a configuration mode, and wherein the second operating mode is a user mode.
14. An integrated circuit (IC), comprising:
a memory module, wherein the memory module stores a configuration image and an associated security key, wherein the configuration image is loaded into the memory module from an external memory module coupled to the IC;
a user logic block coupled to receive a tamper signal;
a core logic block coupled to the user logic block and the memory module, wherein the core logic block transmits configuration instructions through a scan chain interface to overwrite the configuration image with a further configuration image from the external memory module and erase the associated security key from the memory module in response to the tamper signal, wherein the further configuration image configures the IC to transmit an erase signal to erase the configuration image stored in the external memory module; and
a clock source that clocks the configuration instructions sent from the core logic block.
15. The IC of claim 14 further comprising:
a tamper detector circuit coupled to the IC, wherein the tamper detector circuit detects unauthorized access to the IC.
16. The IC of claim 14 , wherein the configuration image is stored in the external memory module, and wherein the configuration image stored in the external memory module configures the IC upon power up.
17. The IC of claim 16 , wherein the external memory module is a non-volatile memory module.
18. The IC of claim 14 , wherein the memory module is a control random access memory (CRAM) module and wherein the IC is a programmable logic device.
19. A device, comprising:
tamper-detect circuitry that identifies unauthorized access to a system;
an integrated circuit (IC) coupled to the tamper-detect circuitry;
a configuration memory module on the IC that stores a configuration image;
a scan chain interface module coupled to the configuration memory module, wherein the scan chain interface module sends configuration instructions to overwrite the configuration image stored in the configuration memory module with a further configuration image from a non-volatile memory module external to the IC, based on signals from the tamper-detect circuitry; and
the non-volatile memory module coupled to the IC, the non-volatile memory module having a copy of the configuration image, wherein the further configuration image configures the IC to transmit an erase signal to erase the copy of the configuration image stored in the non-volatile memory module.
20. The device of claim 19 , wherein the IC includes an internal clock source that clocks the configuration instructions.
21. The device of claim 19 , wherein the configuration memory module includes a security key associated with the configuration image, and wherein the configuration image is an encrypted image.
22. The device of claim 19 , wherein the further configuration image is an unencrypted image.