Sample rate converter
View Patent ↗Techniques and mechanisms implement a sample rate converter for resampling data, such as audio data. The resampling may be based on a resampling clock. As the frequency of the resampling clock varies (e.g., due to jitter, rate adjustment, etc.), a control loop feedback mechanism can detect the variations and gradually correct the sampling rate of the resampled data.
1. A circuit comprising:
a clock period measurement unit to determine a period of a clock signal;
an average clock period calculation unit to determine an average period of the clock signal, the average period of the clock signal based on a plurality of measurements of the period of the clock signal;
a period adjustment unit to generate an adjusted average period of the clock signal based on the average period of the clock signal and one or more adjustment values;
a period difference unit to determine a difference of the adjusted average period of the clock signal and the period of the clock signal; and
an adjustment values unit to generate the one or more adjustment values based on the difference of the adjusted average period of the clock signal and the period of the clock signal.
2. The circuit of claim 1 , wherein the adjusted average period of the clock signal is based on a summation of the average period of the clock signal and the one or more adjustment values.
3. The circuit of claim 1 , wherein the average period clock period calculation unit includes a first accumulator and a second accumulator.
4. The circuit of claim 3 , wherein the first accumulator provides an average period of a first number of periods of the clock signal, and the second accumulator stage provides an average period of a second number of the average periods provided by the first accumulator.
5. The circuit of claim 4 , wherein the second number is higher than the first number.
6. The circuit of claim 4 , wherein the first accumulator generates an enable signal provided to the second accumulator, the second accumulator to store data corresponding with the average period of the of the first number of periods of the clock signal provided by the first accumulator based on the enable signal.
7. The circuit of claim 1 , further comprising:
a timing calculator unit for providing data for resampling an audio signal based on the adjusted average period of the clock signal.
8. A circuit comprising:
an average clock period calculation unit to determine an average period of a clock signal, the average period of the clock signal based on a plurality of measurements of the period of the clock signal; and
a clock control unit to determine a first adjusted average period of the clock signal based on the average period of the clock signal and the period of the clock signal, wherein the clock control unit generates a first adjustment value based on a difference in period of the first adjusted average period of the clock signal and the period of the clock signal.
9. The circuit of claim 8 , further comprising:
a timing calculator unit to provide data for resampling a signal based on the first adjusted average period of the clock signal.
10. The circuit of claim 8 , wherein the clock control unit determines a second adjusted average period of the clock signal based on the average period of the clock signal and the first adjustment value.
11. The circuit of claim 10 , wherein the second adjusted average period of the clock signal is based on a summation of the average period of the clock signal and the first adjustment value.
12. The circuit of claim 11 , wherein the clock control unit determines a second adjustment value based on the second adjusted average period of the clock signal and the period of the clock signal.
13. The circuit of claim 12 , wherein the clock control unit determines a third adjusted average period of the clock signal based on the average period of the clock signal, the first adjustment value, and the second adjustment value.
14. The circuit of claim 8 , wherein the average period clock period calculation unit includes a first accumulator and a second accumulator.
15. The circuit of claim 14 , wherein the first accumulator provides an average period of a first number of periods of the clock signal, and the second accumulator stage provides an average period of a second number of the average periods provided by the first accumulator.
16. The circuit of claim 15 , wherein the second number is higher than the first number.
17. The circuit of claim 15 , wherein the first accumulator generates an enable signal provided to the second accumulator, the second accumulator to store data corresponding with the average period of the of the first number of periods of the clock signal provided by the first accumulator based on the enable signal.
18. A method for resampling a signal, the method comprising:
determining a difference in period between a first adjusted average period of a clock signal and a period of a clock signal;
generating an adjustment value based on the difference in period between the first adjusted average period of a clock signal and the period of a clock signal;
determining an average period of the clock signal; and
generating a second adjusted average period of a clock signal based on the adjustment value and the average period of the clock signal.
19. The method of claim 18 , further comprising:
determining a difference in period between the second adjusted average period of the clock signal and the period of the clock signal; and
generating a second adjustment value based on the difference in period between the second adjusted average period of the clock signal and the period of the clock signal.