IP Library Granted Patent US 8,989,284
Granted Patent B1
US 8,989,284 · App. 13/175,749 · Granted Mar 24, 2015

Method and system for transitioning a communication circuit to a low-power state

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Quick Facts
Patent No.
US 8,989,284
App. No.
13/175,749
Granted
Mar 24, 2015
Kind
B1
Abstract

A method and system for transitioning a communication circuit to a low-power state are disclosed. Where a first device and a second device communicate over a communication link, the first device may initiate a transition from an active state to a low-power state to conserve energy. A symbol may be encoded by the first device in data and transmitted to the second device. The first device may deactivate one or more components when entering the low-power state. Additionally, responsive to receiving and decoding the symbol, the second device may deactivate one or more components when entering the low-power state. In this manner, energy consumption of one or more components can be reduced and a low-power state may be entered to conserve energy.

Claims (37)

1. A method of transitioning a communication circuit to a low-power state, said method comprising:

accessing, at a first communication device, a request to transition said first communication device to said low-power state, wherein said first communication device is operable to communicate with a second communication device over a communication link, and wherein said first communication device is a programmable logic device, wherein said communication link comprises a first data port associated with said first communication device and a second data port associated with said second communication device;

encoding, at said first communication device, a symbol in data, wherein said symbol is associated with said request; and

transmitting said data comprising said symbol from said first communication device to said second communication device to initiate at said second communication device a transition from an active state to said low-power state.

2. The method of claim 1 , wherein said first communication device is a field-programmable gate array (FPGA).

3. The method of claim 1 , wherein said communication link is an Ethernet link.

4. The method of claim 1 , wherein said request comprises a signal presented at a 10 gigabit media independent interface (XGMII) of said first communication device.

5. The method of claim 1 , wherein said symbol is operable to be decoded by said second communication device to initiate a deactivation of at least one component of said second communication device.

6. The method of claim 1 further comprising:

responsive to said transmitting, storing coefficients at said first communication device.

7. The method of claim 6 , wherein said coefficients are adaptive filter coefficients.

8. The method of claim 6 further comprising:

responsive to said storing, deactivating at least one component of said first communication device to transition said first communication device from said active state to said low-power state.

9. The method of claim 8 , wherein at least one component of said second communication device is operable to be deactivated responsive to said deactivating of at least one component of said first communication device.

10. A circuit of a first communication device, said circuit comprising:

a first component operable to access a request to transition said first communication device to a low-power state, wherein said first communication device is operable to communicate with a second communication device over a communication link, wherein said first communication device is a programmable logic device, wherein said first component is further operable to encode a symbol in data, and wherein said symbol is associated with said request, wherein said communication link comprises a first data port associated with said first communication device and a second data port associated with said second communication device;

a second component operable to transmit said data comprising said symbol from said first communication device to said second communication device over said communication link to initiate at said second communication device a transition from an active state to said low-power state; and

a state machine operable to control said first and second components.

11. The circuit of claim 10 , wherein said first communication device is a field-programmable gate array (FPGA).

12. The circuit of claim 10 , wherein said request comprises a signal presented at a 10 gigabit media independent interface (XGMII) of said first communication device.

13. The circuit of claim 10 , wherein said symbol is operable to be decoded by said second communication device to initiate a deactivation of at least one component of said second communication device.

14. The circuit of claim 10 , wherein said state machine is further operable to initiate a storing of coefficients responsive to a transmission of said data comprising said symbol.

15. The circuit of claim 14 , wherein said coefficients are adaptive filter coefficients.

16. The circuit of claim 14 , wherein said state machine is further operable to initiate a deactivation of at least one component of said first communication device responsive to said storing of said coefficients to transition said first communication device from said active state to said low-power state.

17. The circuit of claim 16 , wherein at least one component of said second communication device is operable to be deactivated responsive to said deactivation of at least one component of said first communication device.

18. An integrated circuit comprising:

an encoder of a first communication device operable to access a request to transition said first communication device to a low-power state, wherein said encoder is further operable to encode a symbol in data, wherein said symbol is associated with said request;

a transmitter operable to transmit said data comprising said symbol to a second communication device over a communication link to initiate at said second communication device a transition from an active state to said low-power state, wherein said communication link enables communication with said second communication device, and wherein said communication link comprises a first data port associated with said first communication device and a second data port associated with said second communication device; and

a state machine operable to control said encoder and said transmitter.

19. The integrated circuit of claim 18 further comprising:

a 10 gigabit media independent interface (XGMII), and

wherein said request comprises a signal presented at said XGMII.

20. The integrated circuit of claim 18 , wherein said symbol is operable to be decoded by said second communication device to initiate a deactivation of at least one component of said second communication device.

21. The integrated circuit of claim 18 , wherein said state machine is further operable to initiate a storing of coefficients responsive to a transmission of said data comprising said symbol.

22. The integrated circuit of claim 21 , wherein said coefficients are adaptive filter coefficients.

23. The integrated circuit of claim 21 , wherein said state machine is further operable to initiate a deactivation of at least one component of said first communication device responsive to said storing of said coefficients to transition said first communication device from said active state to said low-power state.

24. The integrated circuit of claim 23 , wherein at least one component of said second communication device is operable to be deactivated responsive to said deactivation of at least one component of said first communication device.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2011
From: VIJAYARAGHAVAN, DIVYA; LEE, CHONG H.
To: ALTERA CORPORATION
Reel/Frame 026930/0582 →