Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter

1. A method of calibrating a successive approximation register (SAR) analog-to-digital converter (ADC), the method comprising:

comparing a capacitance of a first capacitor stage to a sum of capacitances of a plurality of capacitor stages and of a first capacitor array; and

in response to the comparing, increasing the capacitance of the first capacitor stage by increasing the capacitance of a second capacitor array when the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array, wherein the plurality of capacitor stages, the first capacitor array, and the first capacitor stage are coupled in parallel.

2. The method of claim 1 , comprising

repeating the comparing and the increasing until the capacitance of the first capacitor stage exceeds the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

3. The method of claim 2 , comprising

performing a calibration at a second capacitor stage when the capacitance of the first capacitor stage exceeds the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

4. The method of claim 2 , comprising

determining whether the capacitance of the second capacitor array has been increased to a maximum value; and

reducing the capacitance of the first capacitor array when the capacitance of the second capacitor array has been increased to the maximum value, and the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

5. The method of claim 2 , comprising

determining whether the capacitance of the second capacitor array has been increased above a minimum value; and

increasing the capacitance of the first capacitor array when the capacitance of the second capacitor array has not been increased above the minimum value, and the capacitance of the first capacitor stage exceeds the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

6. The method of claim 5 , comprising

repeating the steps of determining whether the capacitance of the second capacitor array has been increased above a minimum value and increasing the capacitance of the first capacitor array until the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

7. The method of claim 6 , comprising

after increasing the capacitance of the first capacitor array until the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array, performing calibration at a starting capacitor stage in the plurality of capacitor stages.

8. The method of claim 1 , wherein the first capacitor array and the second capacitor array each comprise a plurality of capacitors connected in parallel.

9. The method of claim 1 , comprising

storing a counter value, wherein, when the counter value exceeds a threshold value, calibration of the first capacitor stage is halted and calibration of a second capacitor stage is initiated.

10. A system for calibrating a successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising:

a plurality of capacitor stages coupled in parallel;

a first capacitor array coupled in parallel to each of the plurality of capacitor stages;

a first capacitor stage comprising a second capacitor array, the first capacitor stage coupled in parallel with each of the plurality of capacitor stages and with the first capacitor array; and

calibration logic configured to:

compare a capacitance of the first capacitor stage to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array; and

in response to comparing, increase the capacitance of the first capacitor stage by increasing the capacitance of the second capacitor array when the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

11. The system of claim 10 , wherein the calibration logic is configured to repeat the comparing and the increasing until the capacitance of the first capacitor stage exceeds the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

12. The system of claim 11 , wherein the calibration logic is further configured to perform calibration at a second capacitor stage when the capacitance of the first capacitor stage exceeds the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

13. The system of claim 11 , wherein the calibration logic is configured to:

determine whether the capacitance of the second capacitor array has been increased above a minimum value; and

increase the capacitance of the first capacitor array when the capacitance of the second capacitor array has not been increased above the minimum value, and the capacitance of the first capacitor stage exceeds the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

14. The system of claim 13 , wherein the calibration process is configured to repeat the determining whether the capacitance of the second capacitor array has been increased above a minimum value and increasing the capacitance of the first capacitor array until the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

15. The system of claim 14 , wherein the calibration logic is configured to perform calibration at a starting capacitor stage in the plurality of capacitor stages after increasing the capacitance of the first capacitor array until the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

16. The system of claim 10 , wherein the calibration logic is configured to

determine whether the capacitance of the second capacitor array has been increased to a maximum value; and

reduce the capacitance of the first capacitor array when the capacitance of the second capacitor array has been increased to the maximum value, and the capacitance of the first capacitor stage does not exceed the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.

17. The system of claim 10 , wherein the first capacitor array and the second capacitor array each comprise a plurality of capacitors coupled in parallel.

18. The system of claim 10 , wherein the calibration logic is configured to

store a counter value;

halt calibration at the first capacitor stage; and

perform calibration at a second capacitor stage if the counter value exceeds a threshold.

19. A system for calibrating a successive approximation register (SAR) analog to digital converter (ADC) comprising:

digital to analog converter (DAC) circuitry comprising a plurality of capacitor stages coupled in parallel, each capacitor stage coupled in series with a controllable switch associated with the capacitor stage; and

calibration circuitry configured to

calibrate a first capacitor stage of the plurality of capacitor stages by adjusting a capacitance of the first capacitor stage, and

operate the controllable switch associated with the first capacitor stage to connect the first capacitor stage to a reference voltage source or a common mode voltage source, wherein the DAC circuitry comprises a capacitor array and the calibration circuitry is configured to compare via a comparator a capacitance of the first capacitor stage to a sum of capacitances of the other capacitor stages of the plurality of capacitor stages and a capacitance of the capacitor array.

20. A system for calibrating a successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising:

a plurality of capacitor stages coupled in parallel;

a first capacitor array coupled in parallel to each of the plurality of capacitor stages, wherein:

the plurality of capacitor stages comprises a first sub-plurality of capacitor stages and a second sub-plurality of capacitor stages,

a first capacitor stage of the second sub-plurality of capacitor stages comprises a second capacitor array; and

the first sub-plurality of capacitor stages is not calibrated and the second plurality of capacitor stages is calibrated based on capacitances of the first sub-plurality of capacitor stages and of the first capacitor array.

21. The system of claim 20 , further comprising a plurality of switches connected in series with the first capacitor array and with respective ones of the plurality of capacitor stages, each switch of the plurality of switches being configured to selectively connect the first capacitor array and the respective ones of the plurality of capacitor stages to one of a reference voltage and a common mode voltage.

22. The system of claim 21 , further comprising:

calibration logic coupled to the plurality of switches; and

a comparator having an input coupled to each capacitor stage of the plurality of capacitor stages, and an output coupled to the calibration logic.

23. The system of claim 20 , further comprising calibration logic configured to:

compare a capacitance of the first capacitor stage to a sum of the capacitances of the first sub-plurality of capacitor stages and of the first capacitor array; and

in response to comparing, increase the capacitance of the first capacitor stage by increasing the capacitance of the second capacitor array when the capacitance of the first capacitor stage is less than the sum of the capacitances of the first sub-plurality of capacitor stages and of the first capacitor array.