Circuitry and methods for continuous parallel decoder operation
View Patent ↗Syndrome calculation circuitry for a decoder of codewords having a first number of symbols, where the decoder receives a second number of parallel symbols, and where the first number is not evenly divisible by the second number, includes multipliers equal in number to the second number. Each multiplier multiplies a symbol by a coefficient based on a root of a field of the decoder. The multipliers are divided into a number of groups determined as a function of a modulus of the first number and the second number. Adders equal in number to the groups add outputs of multipliers in respective ones of the groups. Accumulation circuitry accumulates outputs of the adders. Output circuitry adds outputs of the adders to an output of the accumulation circuitry to provide a syndrome. Selection circuitry directs outputs of the adders to the accumulation circuitry or the output circuitry, and resets the accumulation circuitry.
1. A method of calculating a syndrome in a decoder of codewords having a first number of symbols, where the decoder receives a second number of symbols in parallel and where the first number is not evenly divisible by the second number, the method comprising:
dividing the second number of symbols into a number of groups determined as a function of a modulus of the first number and the second number;
at each of a plurality of multipliers equal in number to the second number, receiving one of the symbols and multiplying the one of the symbols by a coefficient based on a root of a field of the decoder;
adding, using one or more adders, outputs of the multipliers in each respective one of the groups;
directing outputs of the one or more adders to one or both of accumulation circuitry or output circuitry configured to add the outputs of the one or more adders to an output of the accumulation circuitry to provide a syndrome output; and
resetting the accumulation circuitry when directing the outputs of the one or more adders to the output circuitry.
2. The method of claim 1 , wherein the function of the modulus of the first number and the second number comprises a quotient of the second number and the modulus.
3. The method of claim 1 , wherein the function of the modulus of the first number and the second number comprises a quotient of the second number and a difference between the second number and the modulus.
4. The method of claim 1 , wherein directing the outputs of the one or more adders comprises:
counting by increments of the second number until a value is reached at which the first number is exceeded; and
decoding the value to a selection signal that directs the output of each of the one or more adders to one of the accumulation circuitry or the output circuitry.
5. The method of claim 4 , wherein the output of each of the one or more adders is directed to one of the accumulation circuitry or the output circuitry based at least in part on a logical AND of the selection signal and the respective output of the respective one or more adders.
6. The method of claim 4 , comprising resetting the accumulation circuitry when the value is reached at which the first number is exceeded.
7. The method of claim 4 , comprising adjusting the syndrome output based on the value at which the first number is exceeded.
8. The method of claim 7 , wherein the adjusting comprises:
decoding the value to an index;
using the index to select an adjustment factor from a lookup table; and
adjusting the syndrome output based at least in part on the selected adjustment factor.
9. Machine-readable storage including machine-readable instructions that, when executed, implement the method of claim 1 .