Method and apparatus for performing parallel routing using a multi-threaded routing procedure
A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
1. A method, comprising:
determining a number of available threads to perform operations on nets, wherein a net of the nets defines a connection between one or more cells on a target programmable logic device to implement a circuit; and
performing at least one of the following operations:
a multithreaded timing analysis on the nets;
a multithreaded placement process associated with the nets; and
a multithreaded routing associated with the nets.
2. The method of claim 1 , wherein the one or more cells comprise one or more memory blocks, digital signal processing (DSP) blocks, input/output (I/O) elements, logic blocks, or any combination thereof.
3. The method of claim 1 , wherein the multithreaded routing associated with the nets and the multithreaded timing analysis on the nets are performed.
4. The method of claim 1 , wherein the number of available threads is based at least in part on an operating system corresponding to processors available to route the nets.
5. The method of claim 1 , wherein the number of available threads corresponds directly to a number of processors available to route the nets.
6. The method of claim 1 , comprising simultaneously routing the nets in parallel as part of a multithreading operation.
7. The method of claim 1 , wherein a bounding box is used to respectively identify the nets.
8. A tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause the processor to:
determine a number of threads available to route nets, wherein a net of the nets defines a relationship between one or more cells corresponding to a programmable logic unit on a target programmable logic device to implement a circuit; and
execute the threads of the number of threads such that the nets are routed at a same time.
9. The tangible, non-transitory, and machine-readable medium of claim 8 , wherein the threads are executed by processors, and wherein a number of the processors equals an amount of the threads.
10. The tangible, non-transitory, and machine-readable medium of claim 8 , wherein the instructions are configured to cause the processor to perform a timing analysis on the nets in parallel before executing the threads.
11. The tangible, non-transitory, and machine-readable medium of claim 8 , wherein the one or more cells comprise one or more memory blocks, digital signal processing (DSP) blocks, input/output (I/O) elements, or any combination thereof.
12. The tangible, non-transitory, and machine-readable medium of claim 8 , wherein a respective net of the nets is associated with a bounding box configured to limit usability of a component disposed outside of the respective net.
13. The tangible, non-transitory, and machine-readable medium of claim 8 , wherein
the instructions are configured to cause the processor to partition a programmable fabric to correspond to the number of threads available to route nets, and wherein the number of threads available to route nets is less than a number of processors available to execute the threads.
14. A method, comprising:
identifying a number of threads available to route nets, wherein a net of the nets defines a connection between one or more cells on a target programmable logic device;
transforming the nets simultaneously into a placed and routed design, wherein the nets are independently placed and routed in parallel; and
generating a bit stream based on the placed and routed design.
15. The method of claim 14 , comprising identifying a number of processors to identify the number of threads.
16. The method of claim 14 , comprising performing a timing analysis on the nets in parallel.
17. The method of claim 14 , wherein a net defines a relationship between one or more cells of a circuit, and wherein the one or more cells comprise one or more memory blocks.
18. The method of claim 14 , wherein the transforming the nets simultaneously into a placed and routed design comprises generating one or more bounding boxes around the nets to be routed.
19. The method of claim 18 , wherein a bounding box of the one or more bounding boxes identifies routing resources of a target programmable logic device available for routing the nets.
20. A system, comprising:
memory comprising executable instructions associated with an electronic design automation (EDA) tool configured to design a circuit to be loaded on a target device; and
one or more processors coupled to the memory that, in response to execution of the executable instructions, are configured to:
determine a number of available threads to perform operations on nets, wherein a net of the nets defines a connection between one or more cells on a target programmable logic device to implement a circuit; and
perform at least one of the following operations:
a multithreaded timing analysis on the nets;
a multithreaded placement process associated with the nets; and
a multithreaded routing associated with the nets.
21. A system comprising:
a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause the processor to:
determine a number of threads available to perform operations on nets, wherein a net of the nets defines a connection between one or more cells on a target programmable logic device to implement a circuit; and
perform at least one of the following operations:
a multithreaded timing analysis on the nets;
a multithreaded placement process associated with the nets; and
a multithreaded routing associated with the nets; and
a field programmable gate array (FPGA) configured to be programmed to implement a circuitry design generated based at least in part on the operations performed by the threads on the nets.