Block emulation techniques in integrated circuits
View Patent ↗Techniques for emulating a logic block in an integrated circuit (IC) design are provided. The techniques include identifying a plurality of logic elements that are connectable to formal logic block. These logic elements are connected to perform logic functions associated with the logic block. The logic block may be a physical logic block on one IC design and a non-existent logic block on another IC design. The logic elements and associated connections form an emulated logic block.
1. A method of emulating a logic block in an integrated circuit (IC) design, comprising:
identifying a plurality of smaller logic elements that are connectable to emulate the logic block, wherein the logic block includes a one time programmable (OTP) block, and wherein the plurality of smaller logic elements cannot form a physical OTP block;
flagging each of the plurality of smaller logic elements;
connecting the plurality of logic elements to receive input signals and perform logic functions associated with the logic block converting the integrated circuit design from a first data structure relating to a first integrated circuit device to a second data structure relating to a second integrated circuit device;
identifying that the logic block is needed in the integrated circuit design but does not exist in physical form among a plurality of logic elements available for the second integrated circuit device, wherein the plurality of smaller logic elements are included in the plurality of logic elements; and
placing a boundary around the plurality of smaller logic elements to form an emulated logic block based on the logic block, wherein at least one method operation is executed through a processor.
2. The method of claim 1 , wherein the logic block is a physical logic block in another IC design, and wherein the logic block is a non-existent block in the IC design.
3. The method of claim 1 , wherein the flagging tags each of the plurality of smaller logic elements as an element in the emulated logic block.
4. The method of claim 1 , further comprising:
determining a hierarchy of the logic block to be emulated before the determining of the plurality of smaller logic elements.
5. The method of claim 1 , wherein the emulated logic block comprises an equal number of input and output terminals with the logic block.
6. The method of claim 1 , wherein the emulated logic block and the logic block are functionally equivalent.
7. The method of claim 1 , further comprising:
arranging same terminals on the boundary of the emulated logic block as on a boundary of the logic block.
8. The method of claim 1 , wherein the plurality of smaller logic elements includes a shift register, and wherein the connecting applies the shift register to emulating the one time programmable block.
9. The method of claim 1 , wherein the plurality of smaller logic elements includes, and the connecting applies to emulating the one time programmable block, one of: a counter, a read only memory (ROM) block, or a lookup table (LUT).
10. A non-transitory machine-readable storage medium encoded with sequences of instructions for emulating a logic block in an integrated circuit (IC) design, the sequences of instructions which when executed, cause a machine to perform:
identifying a plurality of smaller logic elements that are connectable to emulate the logic block, the logic block having a one time programmable (OTP) block, the plurality of smaller logic elements unable to form a physical OTP block;
flagging each of the plurality of smaller logic elements;
connecting the plurality of logic elements to receive input signals and perform logic functions associated with the logic block converting the integrated circuit design from a first data structure relating to a first integrated circuit device to a second data structure relating to a second integrated circuit device;
identifying that the logic block is needed in the integrated circuit design but does not exist in physical form among a plurality of logic elements available for the second integrated circuit device, wherein the plurality of smaller logic elements are included in the plurality of logic elements; and
placing a boundary around the plurality of smaller logic elements to form an emulated logic block based on the logic block.
11. The computer readable medium of claim 10 , wherein the logic block is a physical logic block in another IC design, and wherein the logic block is a non-existent block in the IC design.
12. The computer readable medium of claim 10 , wherein the flagging tags each of the plurality of smaller logic elements as an element in the emulated logic block.
13. The computer readable medium of claim 10 , further comprising:
determining a hierarchy of the logic block to be emulated before the determining of the plurality of smaller logic elements.
14. The computer readable medium of claim 10 , wherein the emulated logic block comprises an equal number of input and output terminals with the logic block.
15. The computer readable medium of claim 10 , wherein the emulated logic block and the logic block are functionally equivalent.
16. The computer readable medium of claim 10 , wherein the IC design is for a programmable logic device.
17. The computer readable medium of claim 10 , wherein the emulated logic block has keypoints that match keypoints of the logic block.
18. The computer readable medium of claim 10 , wherein the connecting applies, in emulating the one time programmable block, and the plurality of smaller logic elements includes, one of: a shift register, a counter, a read only memory (ROM) block, or a lookup table (LUT).