Method and apparatus for performing incremental compilation using structural netlist comparison

1. A system, comprising:

a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed, cause a processor to:

compare a first netlist and a second netlist to determine a matching subset of cells between the first netlist and the second netlist, wherein the first netlist corresponds to a previously optimized netlist for a first hardware description language design, wherein the second netlist corresponds to a second hardware description language design having one or more portions different from the first hardware description language design, and wherein the comparison is based at least in part on a routing of fanouts between the cells;

identify a portion of the first netlist as matching based at least in part on the matching subset of the cells;

generate a programmable logic circuit placement for the second netlist at least in part by reusing placement of the portion of the first netlist identified as matching; and

generate a bit stream based at least in part on the programmable logic circuit placement, wherein the bit stream is configured to cause programming of the second hardware description language design into components of a programmable logic; and

a field programmable gate array configured to be programmed to implement the second hardware description language design based at least in part on the bit stream generated in response to operations performed to identify the portion of the first netlist eligible to be reused.

2. The system of claim 1 , wherein the machine-readable instructions that, when executed, cause the processor to determine the matching subset of the cells between the first netlist and the second netlist also comprise instructions that cause the processor to determine the matching subset of the cells based at least in part on a comparison between a first fanout of the first netlist and a second fanout of the second netlist, wherein the first fanout comprises a first routing segment into a second routing segment and a third routing segment.

3. The system of claim 1 , wherein the machine-readable instructions that, when executed, cause the processor to generate the bit stream based at least in part on the programmable logic circuit placement also comprise instructions that cause the processor to perform one or more incremental placements and routings based at least in part on the matching subset of the cells.

4. The system of claim 1 , wherein the machine-readable instructions that, when executed, cause the processor to identify the portion of the first netlist for reuse based at least in part on the matching subset of the cells also comprise instructions that cause the processor to identify the portion of the first netlist for reuse at least partially simultaneous to another operation.

5. The system of claim 1 , wherein the machine-readable instructions that, when executed, cause the processor to determine the matching subset of the cells between the first netlist and the second netlist also comprise instructions that cause the processor to identify the matching subset of the cells based at least in part on pins between the first netlist and the second netlist.

6. The system of claim 1 , wherein the machine-readable instructions that, when executed, cause the processor to generate the programmable logic circuit placement for the second netlist at least in part by reusing the portion of the first netlist also comprise instructions that cause the processor to generate the programmable logic circuit placement for the second netlist without repeating a physical optimization of the portion of the first netlist eligible to be reused.

7. The system of claim 1 , wherein the portion of the first netlist is identified based at least in part on a placement of a first routing segment relative to a second routing segment.