Dynamically scalable timing and power models for programmable logic devices
Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.
1. A system comprising:
a programmable logic device configurable to execute a number of operations;
a number of voltage libraries defining predetermined voltage levels for analysis of the programmable logic device;
a scaler configured to:
determine an operating voltage of the programmable logic device;
receive a voltage correction factor based at least in part on the operating voltage of the programmable logic device; and
determine an interpolated voltage for the programmable logic device based on the operating voltage of the programmable logic device, the voltage correction factor, and at least one of the predetermined voltage levels; and
an analysis engine configured to determine an amount of slack for a particular workload of the programmable logic device at the interpolated voltage.
2. The system of claim 1 , wherein the scaler is configured to determine an updated voltage level for the programmable logic device based on the amount of slack at the interpolated voltage and wherein the slack is associated with a timing slack or a power slack of the programmable logic device at the interpolated voltage.
3. The system of claim 1 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).
4. The system of claim 1 , wherein the number of voltage libraries comprise power, voltage, and temperature conditions for the programmable logic device.
5. The system of claim 1 , wherein the analysis engine comprises a timing analyzer and a power analyzer.
6. The system of claim 5 , wherein the timing analyzer and the power analyzer are configured to determine the amount of slack for a particular workload of the programmable logic device at the operating voltage of the programmable logic device.
7. The system of claim 1 , wherein the scaler is configured to determine an updated voltage level for the programmable logic device based on the amount of slack at the operating voltage of the programmable logic device.
8. The system of claim 7 , wherein a model generator is configured to generate a voltage library for the interpolated voltage.
9. The system of claim 7 , wherein the updated voltage level is determined by interpolating between two of the predetermined voltage levels for corresponding voltage libraries of the number of voltage libraries.
10. A method comprising:
determining a voltage level of a programmable logic device;
identifying a plurality of voltage libraries each defining a predetermined voltage level for analysis of the programmable logic device;
comparing the voltage level of a programmable logic device to the predetermined voltage levels of the plurality of voltage libraries;
identifying a first voltage level of the predetermined voltage levels and a second voltage level of the predetermined voltage levels, the first voltage level closest to and greater than the voltage level of the programmable logic device, the second voltage level closest to and less than the voltage level of the programmable logic device;
generating an interpolated voltage level for the programmable logic device based at least in part on the first voltage level and the second voltage level; and
generating a timing and power model for the programmable logic device based on the interpolated voltage level.
11. The method of claim 10 , comprising:
analyzing the timing and power model for the programmable logic device based at least in part on the timing and power model; and
determining an amount of slack for at least one of a timing and power of the programmable logic device at the interpolated voltage level.
12. The method of claim 10 , comprising analyzing the programmable logic device at the interpolated voltage level using the timing and power model.
13. The method of claim 10 , comprising obtaining a voltage correction factor, wherein the interpolated voltage level is based at least in part on the voltage correction factor.
14. The method of claim 10 , wherein the interpolated voltage level is determined by interpolating between the first voltage level and the second voltage level.
15. The method of claim 10 , comprising:
determining the voltage level of a programmable logic device matches a predetermined voltage level of a first voltage library of the plurality of voltage libraries;
generating a timing and power model for the programmable logic device based on the first voltage library; and
analyzing the programmable logic device at the first voltage level using the timing and power model based on the first voltage library.
16. A device comprising:
configuration memory configured to store a plurality of voltage libraries defining predetermined voltage levels;
a programmable logic configured to perform a first operation based on at least one predetermined voltage level of the voltage libraries; and
control circuitry configured to:
instruct the programmable logic to perform the first operation; and
while the programmable logic performs the first operation:
receive a first voltage value;
receive a voltage correction factor based at least in part on the first voltage value;
determine a slack associated with the at least one predetermined voltage level;
generate an updated voltage value for the programmable logic based at least in part on the slack and the voltage correction factor; and
upon determining that the slack is near zero, generating a timing and/or power model for the programmable logic at the updated voltage value.
17. The device of claim 16 , wherein the updated voltage value is determined by interpolating between two voltage libraries of the plurality of voltage libraries to generate an interpolated voltage.
18. The device of claim 17 , wherein the slack indicates a difference between a frequency and/or power of the device at the at least one predetermined voltage level and a target frequency and/or power of the device.
19. The device of claim 17 , the control circuitry configured to analyze the programmable logic based on the timing and/or power model using the interpolated voltage.
20. The device of claim 17 , the control circuitry configured to generate a voltage library based at least in part on the updated voltage value.