Variable precision floating-point multiplier
Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be wide enough to handle the required precision of the mantissa. In a bridged mode, the first CPA may borrow an additional bit from the second CPA while the rounding circuit will monitor the appropriate bits to select the proper multiplier output. A parallel prefix tree operable in a non-bridged mode or the bridged mode may be used to compute multiple multiplier outputs. The multiplier circuit may also include exponent and exception handling circuitry using various masks corresponding to the desired precision width.
1. Multiplier circuitry on an integrated circuit die, comprising:
a partial product generator configured to receive a first input signal and a second input signal;
a compressor tree circuit configured to receive signals from the partial product generator and to generate a first set of sum and carry vectors and a second set of sum and carry vectors; and
carry propagate adder circuitry configured to receive the first set of sum and carry vectors and the second set of sum and carry vectors from the compressor tree circuit, wherein the carry propagate adder circuitry is configured to output multiplier output values each having an exponent with an exponent width varying continuously within a range from a first integer value to a second integer value.
2. The multiplier circuitry of claim 1 , wherein the first integer value is 5.
3. The multiplier circuitry of claim 2 , wherein the second integer value is 9.
4. The multiplier circuitry of claim 3 , wherein the exponents of the multiplier output values is equal to 5 in a first mode.
5. The multiplier circuitry of claim 4 , wherein the exponents of the multiplier output values is equal to 6 in a second mode.
6. The multiplier circuitry of claim 5 , wherein the exponents of the multiplier output values is equal to 7 in a third mode.
7. The multiplier circuitry of claim 6 , wherein the exponents of the multiplier output values is equal to 8 in a fourth mode.
8. The multiplier circuitry of claim 7 , wherein the exponents of the multiplier output values is equal to 9 in a fifth mode.
9. The multiplier circuitry of claim 2 , wherein the second integer value is 8.
10. The multiplier circuitry of claim 1 , wherein the first input signal has a first exponent, and wherein the second input signal has a second exponent that is different than the first exponent.
11. The multiplier circuitry of claim 10 , further comprising:
exponent handling circuitry configured to combine the first exponent with the second exponent based on an adjustable bias value that varies as a function of the precision of the first and second exponents.
12. The multiplier circuitry of claim 11 , wherein the exponent handling circuitry is further configured to combine the first exponent with the second exponent based on an adjustable normalization value.
13. The multiplier circuitry of claim 12 , wherein first exponent has 8 bits.
14. The multiplier circuitry of claim 12 , wherein first exponent has 5 bits.
15. The multiplier circuitry of claim 11 , wherein the first input signal number has a number of mantissa bits that is adjusted based on the first exponent.
16. The multiplier circuitry of claim 1 , wherein the multiplier output values have a mantissa size that is adjusted based on the exponents.
17. The multiplier circuitry of claim 16 , wherein the multiplier circuitry has a rounding position that shifts as the mantissa size is adjusted.
18. The multiplier circuitry of claim 1 , further comprising:
exponent exception handling circuitry that includes a logic gate mask that varies depending on the value of the exponents.
19. The multiplier circuitry of claim 18 , wherein the logic gate mask comprises a logic AND mask used to detect whether the multiplier output values are zero.
20. The integrated circuit of claim 18 , wherein the logic gate mask comprises a logic OR mask used to detect whether the multiplier output values are infinity or a number divided by zero.