Parallel CRC calculation for multiple packets without requiring a shifter
Systems and methods are provided herein for removing the need to account for varying lengths of data packets that are transmitted during a single clock cycle, and to require only one CRC calculation block for handling parallel processing of a stream of data packets received during a clock cycle. Moreover, systems and methods are provided herein for eliminating a need for a shifter, such as a barrel shifter, to process the data packets of a single clock cycle in parallel.
1. A programmable integrated circuit device for parallel calculation of cyclic redundancy check (“CRC”) values for a plurality of packets received in a clock cycle, the programmable integrated circuit device comprising:
a padding bit-replacement block configured to:
receive a stream comprising the plurality of packets, wherein the plurality of packets have N packets;
generate N copies of the stream, wherein each copy of the stream is associated with a respective packet of the plurality of packets; and
for each respective copy of the N copies of the stream, replace with padding bits all packets but the respective packet associated with the respective copy to create a respective padded copy of a plurality of padded copies;
a CRC calculation block configured to:
receive the plurality of padded copies; and
calculate a packet CRC value for each packet of the plurality of packets to form a plurality of packet CRC values by calculating a respective CRC value for each respective padded copy of the plurality of padded copies; and
a matrix reverse block configured to iteratively merge each padded copy of the plurality of padded copies by removing the padding bits from each padded copy of the plurality of padded copies to produce a reformed stream.
2. The programmable integrated circuit device of claim 1 , wherein the matrix reverse block is configured to append each respective packet CRC value to the respective packet of the reformed stream.
3. The programmable integrated circuit device of claim 1 , wherein the matrix reverse block is configured to perform N matrix reverse operations.
4. The programmable integrated circuit device of claim 1 , wherein the CRC calculation block is configured to calculate each respective packet CRC value by using a lookup table to determine values of padding bits to the left of the respective packet in the respective padded copy.
5. The programmable integrated circuit device of claim 1 , wherein the CRC calculation block is configured to calculate plurality of packet CRC values from the plurality of padded copies in parallel.
6. The programmable integrated circuit device of claim 1 , wherein the padding bits are all either zeros or ones for all padded copies of the plurality of padded copies.
7. The programmable integrated circuit device of claim 1 , wherein the stream is received during one single clock cycle.
8. A method for parallel calculation of cyclic redundancy check (“CRC”) values for a plurality of packets received in a clock cycle, the method comprising:
receiving a stream comprising a first number of packets in replicating and padding circuitry;
generating a plurality of copies of the stream, wherein each copy of the stream of copies is associated with a packet of the stream;
modifying each copy of the plurality of copies to generate a modified copy of a plurality of modified copies by, for each respective copy of the plurality of copies, replacing all packets of the respective copy of the stream but the respective associated packet with padding bits to generate a respective modified copy;
transmitting the plurality of modified copies to a CRC calculation block;
calculating, at the CRC calculation block, a respective CRC value associated with each packet of the stream by performing a CRC operation for each respective modified copy of the plurality of modified copies;
transmitting, from the CRC calculation block, the plurality of modified copies to a matrix reverse block; and
generating, at the matrix reverse block, restored data stream by iteratively merging the plurality of modified copies, wherein the iterative merging of the plurality modified copies comprises removing the padding bits from each modified copy of the plurality of modified copies.
9. The method of claim 8 , comprising appending to each respective packet the respective calculated CRC value at the matrix reverse block.
10. The method of claim 8 , wherein iteratively merging the plurality of modified copies comprises performing matrix reverse operations.
11. The method of claim 8 , comprising calculating, at the CRC calculation block, each respective CRC value by using a lookup table to determine values of padding bits to the left of the respective packet in the respective modified copy.
12. The method of claim 8 , comprising calculating, at the CRC calculation block, each respective CRC value for each respective modified copy of the plurality of modified copies in parallel.
13. The method of claim 8 , wherein the padding bits are all either zeros or ones.
14. The method of claim 8 , wherein the plurality of packets comprise data packets or data packet segments or both received during one single clock cycle.
15. A non-transitory machine-readable medium comprising memory with instructions configured to cause data processing circuitry to perform parallel calculation of cyclic redundancy check (“CRC”) values for a plurality of packets received in a clock cycle, wherein the instructions cause the data processing circuitry to:
receive a stream having a first number of packets at a padding bit-replacement block of the data processing circuitry;
generate, at the padding bit-replacement block, a plurality of copies of the stream having the first number of copies, wherein each respective copy is associated with one corresponding packet of the stream;
modify, at the padding bit-replacement block, each respective copy of the plurality of copies to form a plurality of modified copies by replacing all packets but the respective packet associated with the respective copy with padding bits to generate a respective modified copy associated with the respective packet;
transmit the plurality of modified copies to a CRC calculation block of the data processing circuitry;
calculate, at the CRC calculation block, a respective CRC value for each respective packet by calculating the CRC of the respective modified copy associated with the respective packet;
transmit, from the CRC calculation block, the plurality of modified copies to a matrix reverse block of the data processing circuitry; and
generate, at the matrix reverse block, a reformed data stream by iteratively merging each modified copy of the plurality of modified copies by removing the padding bits from each modified copy of the plurality of modified copies.
16. The non-transitory machine-readable medium of claim 15 , comprising instructions configured to cause the matrix reverse block to append to the reformed data stream each calculated CRC value.
17. The non-transitory machine-readable medium of claim 15 , wherein the matrix reverse block comprises matrix reverse operations performed a number of times equal to the first number.
18. The non-transitory machine-readable medium of claim 15 , comprising instructions configured to cause the CRC calculation block to calculate each respective CRC value by using a lookup table to determine values of padding bits to the left of the respective packet in the respective associated modified copy.
19. The non-transitory machine-readable medium of claim 15 , comprising instructions configured to cause the CRC calculation block to calculate the respective CRC values in parallel.
20. The non-transitory machine-readable medium of claim 15 wherein the stream comprises data packets or data packet segments or both received during one single clock cycle.