Low-power routing multiplexers
View Patent ↗Low-power routing multiplexers that reduce static and dynamic power consumption are provided. A variety of different techniques are used to reduce power consumption of the routing multiplexers without significantly increasing their size. For example, power consumption of the routing multiplexers may be reduced by reducing short-circuit currents, reducing leakage currents, limiting voltage swing, and recycling charge within the multiplexer. Multiple power reduction techniques may be combined into a single routing multiplexer design. Low-power routing multiplexers may also be designed to operate in selectable modes, such as, a high-speed, high-power mode and a low-speed, low-power mode.
1. Routing driver multiplexer circuitry comprising:
a multiplexer; and
a buffer circuit comprising:
a first stage, comprising a first circuit and a second circuit, both circuits receiving an output signal from the multiplexer and wherein the first circuit is skewed towards a higher trip point than the second circuit;
a second stage having first and second inputs for respectively receiving first and second output signals from the first and second circuits, wherein the second stage further comprises voltage limiting circuitry operative to limit a voltage swing of the output signal from the multiplexer, and wherein the voltage limiting circuitry comprises at least two transistors in series coupled to the output signal from the multiplexer; and
pull-up circuitry adapted to pull up the output signal from the multiplexer output in response to one of the first and second circuits.
2. The routing driver multiplexer circuitry of claim 1 wherein a PMOS to NMOS ratio of the first circuit is greater than a PMOS to NMOS ratio of the second circuit.
3. The routing driver multiplexer circuitry of claim 1 further comprising buffer disable circuitry operative to disable the second stage.
4. The routing driver multiplexer circuitry of claim 3 further comprising a control input operative to control the buffer disable circuitry to enable and disable the buffer.
5. The routing driver multiplexer circuitry of claim 1 further comprising a control input operative to enable and disable the voltage limiting circuitry, wherein the buffer circuit is configured to operate in a low-power mode in response to enabling the voltage limiting circuitry and wherein the buffer circuit is configured to operate in a high-power mode in response to disabling the voltage limiting circuitry.
6. The routing driver multiplexer circuitry of claim 1 wherein the voltage limiting circuitry is operable to reduce a high voltage output of the second inverting stage.
7. The routing driver multiplexer circuitry of claim 1 wherein the voltage limiting circuitry is operable to increase a low voltage output of the second stage.
8. The routing driver multiplexer circuitry of claim 1 wherein the voltage limiting circuitry is operable to reduce a high voltage output of the second stage at least by a threshold voltage of an NMOS transistor.
9. Routing driver multiplexer circuitry comprising:
a multiplexer; and
a buffer circuit comprising:
a first inverting stage comprising a first inverter circuit and a second inverter circuit, both inverter circuits receiving an output signal from the multiplexer, wherein the first and second inverter circuits each comprise an NMOS transistor and a PMOS transistor and wherein the first inverter circuit is skewed towards a higher trip point than the second inverter circuit;
a second inverting stage comprising a PMOS transistor, an NMOS transistor, and an output, the PMOS transistor operable to receive an output signal from the first inverter circuit and to pull up a voltage of the output signal from the multiplexer in response to the output signal from the first inverter circuit, and the NMOS transistor operable to receive an output signal from the second inverter circuit and to pull down the voltage of the output signal from the multiplexer in response to the output signal from the second inverter circuit, wherein the second inverting stage further comprises voltage limiting circuitry operative to limit a voltage swing of the output signal from the multiplexer, and wherein the voltage limiting circuitry comprises at least two transistors in series coupled to the output signal from the multiplexer; and
a pull-up transistor adapted to pull up the voltage of the output signal from the multiplexer in response to one of the output signal from the first inverter circuit and the output signal from the second inverter circuit.
10. The routing driver multiplexer circuitry of claim 9 wherein a ratio of PMOS transistor size of the first inverter circuit to NMOS transistor size of the first inverter circuit is greater than a ratio of PMOS transistor size of the second inverter circuit to NMOS transistor size of the second inverter circuit.
11. The routing driver multiplexer circuitry of claim 9 wherein a voltage of the output signal from the second inverter is lower than a voltage of the output signal from the first inverter circuit during a transition of the second inverting stage.
12. The routing driver multiplexer circuitry of claim 9 further comprising buffer disable circuitry operable to prevent the second inverting stage from turning on.
13. The routing driver multiplexer circuitry of claim 12 wherein the buffer disable circuitry comprises a first transistor operable to prevent the output signal from the first inverter circuit from being pulled down and a second transistor operable to pull up the output signal from the first inverter circuit.
14. The routing driver multiplexer circuitry of claim 13 wherein the first and second transistors are controllable to enable and disable the buffer disable circuitry.
15. The routing driver multiplexer circuitry of claim 9 wherein the voltage limiting circuitry is coupled to an input of the second inverting stage and the output of the second inverting stage.
16. The routing driver multiplexer circuitry of claim 9 wherein the voltage limiting circuitry comprises a voltage limiting NMOS transistor coupled to the PMOS transistor of the second inverting stage and the output of the second inverting stage.
17. The routing driver multiplexer circuitry of claim 9 wherein the voltage limiting circuitry comprises a voltage limiting PMOS transistor coupled to the NMOS transistor of the second inverting stage and the output of the second inverting stage.
18. The routing driver multiplexer circuitry of claim 9 wherein the voltage limiting circuitry further comprises a transistor operable to disable one of the inverter circuits of the first inverting stage.
19. The routing driver multiplexer circuitry of claim 9 wherein the voltage limiting circuitry further comprises a control input operable to activate and de-activate the voltage limiting circuitry, wherein the buffer circuit is configured to operate in a low-power mode in response to activating the voltage limiting circuitry and wherein the routing driver multiplexer circuitry is configured to operate in a high-power mode in response to de-activating the voltage limiting circuitry.
20. A method for reducing the power consumption of a routing driver multiplexer circuit comprising:
receiving an output signal from a multiplexer at each of a first and second circuits of a first routing driver multiplexer circuit buffer stage, wherein the first circuit is skewed toward a higher trip point than the second circuit;
receiving a first and a second output signals from the first and the second circuit respectively at a second routing driver multiplexer circuit buffer stage having a first input to receive the first output signal and a second input to receive the second output;
limiting a voltage swing of the output signal from the multiplexer using voltage limiting circuitry that comprises at least two transistors in series coupled to the output signal from the multiplexer; and
pulling up the output signal from the multiplexer in response to at least one of the output signals of the first and second circuits.
21. The method of claim 20 further comprising selectively disabling the second routing driver multiplexer circuit buffer stage.
22. The method of claim 20 further comprising limiting the voltage swing of an output of the second routing driver multiplexer circuit buffer stage in response to a control input, wherein the control input is operable to switch the buffer circuit between a low-power mode and a high-power mode.
23. The method of claim 20 wherein the limiting comprises reducing a high voltage output of the second routing driver multiplexer circuit buffer stage.
24. The method of claim 20 wherein the limiting comprises increasing a low voltage output of the second routing driver multiplexer circuit buffer stage.
25. The method of claim 20 wherein the limiting comprises reducing the high voltage output of the second routing driver multiplexer circuit buffer stage at least by a threshold voltage of an NMOS transistor.