Micro-granular delay testing of configurable ICs

1. An integrated circuit (IC) comprising:

a plurality of configurable circuits, each configurable circuit for configurably performing operations according to a configuration data set;

a launch element for providing a set of test stimulus;

a capture element for capturing a set of responses to the set of test stimulus by a circuitry under test, wherein the circuitry under test comprises a set of the plurality of configurable circuits configured to perform a set of operations in a user mode; and

a debug network for retrieving the captured set of responses.

2. The IC of claim 1 further comprising a plurality of signal lines for supplying at least a clock signal and a control signal that allow the IC to operate in the user mode while the circuitry under test is stimulated by the set of test stimulus.

3. The IC of claim 1 , wherein the launch element comprises at least one of a configurable look-up table, a configurable storage element, and a configurable multiplexer.

4. The IC of claim 1 , wherein the capture element comprises a latch that is controlled by a configuration data set, wherein the configuration data set causes the latch to pass data in one operation cycle and hold data in an immediate subsequent operation cycle.

5. The IC of claim 4 , wherein the data held in the latch is retrieved for analysis using the debug network.

6. The IC of claim 1 , wherein the plurality of configurable circuits comprises a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a plurality of configurable routing circuits for configurably passing signals among circuits of the IC, and a plurality of controllable storage elements for controllably storing signals as the signals transit between the circuits of the IC.

7. The IC of claim 1 , wherein the captured set of responses are used to determine whether the circuitry under test satisfies a set of evaluation criteria.

8. An integrated circuit (IC) comprising:

a first set of configurable circuits for providing a test stimulus;

a second set of configurable circuits for performing a set of operations in a user mode based on the test stimulus;

a third set of configurable circuits for capturing a set of output values produced by the second set of configurable circuits while performing the set of operations; and

a debug network for accessing the set of output values captured in the third set of configurable circuits.

9. The IC of claim 8 further comprising a plurality of signal lines for supplying at least a clock signal and a control signal that allow the IC to operate in the user mode while the second set of configurable circuits is stimulated by the set of test stimulus.

10. The IC of claim 8 , wherein the first set of configurable circuits comprises at least one of a configurable look-up table, a configurable storage element, and a configurable multiplexer.

11. The IC of claim 8 , wherein the second set of configurable circuits comprises a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a plurality of configurable routing circuits for configurably passing signals among circuits of the IC, and a plurality of controllable storage elements for controllably storing signals as the signals transit between the circuits of the IC.

12. The IC of claim 8 , wherein the third set of configurable circuits comprises a latch that is controlled by a configuration data set, wherein the configuration data set causes the latch to pass data in one operation cycle and hold data in an immediate subsequent operation cycle.

13. The IC of claim 12 , wherein the data held in the latch is retrieved for analysis using the debug network.

14. The IC of claim 8 , wherein the second and third sets of configurable circuits are for performing other operations in addition to respectively performing the set of operations in the user mode based on the test stimulus and capturing the set of output values produced by the second set of configurable circuits in response to the test stimulus.

15. A non-transitory computer readable medium storing sets of configuration data for configuring an integrated circuit (IC) to test a set of circuitry in the IC, the IC comprising a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a plurality of configurable routing circuits for configurably passing signals among the circuits of the IC, a plurality of controllable storage elements for controllably storing signals as the signals transit between the configurable circuits, and a debug network that accesses the controllable storage elements, the sets of configuration data comprising:

a set of configuration data for configuring the IC to operate in a user mode, the configured IC having a set of test paths, each test path comprising a set of configurable logic circuits, a set of configurable routing circuits, and at least one controllable storage element; and

a set of configuration data for configuring the debug network to read values stored in storage elements along the set of test paths to determine whether the set of circuitry in the IC is operating within specified performance limits according to a set of test criteria.

16. The non-transitory computer readable medium of claim 15 , wherein the set of configuration data further comprises:

a set of configuration data for configuring a set of configurable circuits for providing a test stimulus to the set of test paths; and

a set of configuration data for configuring the controllable storage elements along the set of test paths for capturing a set of output values produced by the set of test paths.

17. The non-transitory computer readable medium of claim 15 , wherein at least one controllable storage element is a configurable storage element for controllably storing a signal that the storage element receives based on a set of configuration data supplied to the storage element.

18. The non-transitory computer readable medium of claim 15 , wherein the set of test criteria comprises a set of timing constraints.

19. The non-transitory computer readable medium of claim 15 , wherein the set of test criteria comprises a set of expected logic values.

20. A non-transitory computer readable medium storing sets of configuration data for configuring an integrated circuit (IC) comprising a plurality of configurable logic circuits for configurably performing a plurality of logic operations, a configurable routing fabric for passing signals among the circuits of the IC, a plurality of configurable storage elements placed throughout the configurable routing fabric for controllably storing signals passed along the configurable routing fabric, and a debug network that accesses the configurable storage elements, the sets of configuration data comprising:

a set of configuration data for configuring a first set of configurable circuits to operate as a launch element;

a set of configuration data for configuring a second set of configurable circuits to operate as a capture element;

a set of configuration data for defining a set of circuitry in the IC as a set of test paths, wherein each test path is stimulated by a particular configurable circuit in the launch element and terminated at a particular configurable circuit in the capture element.

21. The non-transitory computer readable medium of claim 20 , wherein the set of configuration data configuring the first set of configurable circuits to operate as the launch element comprises a set of instructions for receiving a set of test vectors and for providing a set of stimulus to the set of test paths based on the received test vectors.