Method and circuit for scalable cross point switching using 3-D die stacking
View Patent ↗A cross-point switch having stacked switching dies on a component die is disclosed. The cross point switch allows scalability by adding switching dies. The switching dies include ingress switches that are coupled to multiplexers to a middle stage switches. The inputs and outputs of the ingress switches are connected to the switching interface region via through silicon vias (TSVs). The outputs of the ingress switches are also coupled by TSVs to multiplexers for routing to middle stage switches on a switching die above. If the switching die is stacked on another switching die, the outputs of the ingress switches are coupled by TSVs to the multiplexers for routing to the middle stage switches of the switching die below. By adding switching dies, the switch is configurable to increase the number of ports as well as the width of the ports.
1. A configurable cross point switching system comprising:
a component die including logic components and a switching interface region to allow connection of the logic components;
a first switching die located on the component die, the first switching die including an ingress stage switch having an input and an output and a middle stage switch having an input;
a multiplexer having an input coupled to the output of the ingress stage switch and an output coupled to the input of the middle stage switch;
an input through-silicon via (TSV) coupled between an input port in the switching interface region and the input of the ingress stage switch; and
a second input TSV coupled between a second input port in the switching interface region of the component die and another input of the multiplexer.
2. The switching system of claim 1 , wherein the switching system is configured to select a connection to the middle stage switch from the inputs of the multiplexer.
3. The switching system of claim 1 , wherein the multiplexer is located on the first switching die.
4. The switching system of claim 3 further comprising:
a second switching die stacked on top of the first switching die, the second switching die including an ingress stage switch with an input and an output coupled to an input of a multiplexer and a middle stage switch coupled to the output of the multiplexer; and
an input TSV coupled between a port in the interconnection interface region and the input of the ingress stage switch;
a first switching die input TSV coupled between the output of the ingress stage switch of the first switching die and another input of the multiplexer of the second switching die, wherein the switching system is configured to select a connection to the middle stage switch of the second switching die via the inputs of the multiplexer of the second switching die; and
a second switching die input TSV coupled between the output of the ingress stage switch of the second switching die and another input of the multiplexer of the first switching die.
5. The switching system of claim 4 , wherein the multiplexers of the first and second switching dies are configured to select a predetermined number of input ports on the switching interface region as switch inputs and a predetermined number of output ports on the switching interface regions as switch outputs.
6. The switching system of claim 5 , wherein the switching system is configured via the multiplexers of the first and second switching dies to create a wide channel bit length port by assigning the multiple inputs of the egress switches of the first and second switching dies to a single input port.
7. The switching system of claim 1 , wherein the ingress stage switch, the middle stage switch and the multiplexer are fixed circuitry.
8. The switching system of claim 1 , wherein the interconnection interface region includes programmable logic to select between the first and second input ports.
9. The switching system of claim 8 , wherein the configuration of the interconnection interface region is generated on FPGA logic of the component die, the configuration information transmitted via interconnections to the multiplexer.
10. The switching system of claim 1 , further comprising a processor to program the connections to the input of the middle switch via the multiplexer.
11. The switching system of claim 1 , further comprising:
a first output TSV coupling the output of the ingress stage switch to a first output port in the interconnection interface region; and
a second output TSV coupling the output of the middle stage switch to a second output port in the interconnection interface region.
12. The switching system of claim 1 , wherein the switching system is configured via the multiplexers of the first and second switching dies to conform to the Ethernet physical coding sublayer protocol.
13. The switching system of claim 1 , wherein the switching system is configured via the multiplexers of the first and second switching dies to accommodate inputs according to the Interlaken interface protocol.
14. A method of configuring a cross point switch for cross connections of components on a component die, the method comprising:
adding a first switching die over the component die, the first switching die including a plurality of ingress stage switches cross connected to multiplexers having outputs coupled to the inputs of a plurality of middle stage switches;
coupling an input port to the inputs of the ingress switches of the first switching die; and
controlling the multiplexers to select the inputs from the input port or the outputs of the ingress stage switch for the middle stage switch.
15. The method of claim 14 , further comprising expanding the input ports of the cross point switch by:
adding a second switching die over the first switching die, the first switching die including a plurality of ingress stage switches cross connected to multiplexers having outputs coupled to the inputs of a plurality of middle stage switches;
coupling an input port to the inputs of the ingress switches of the second switching die;
cross coupling some of the outputs of the ingress switches of the first switching die to the multiplexers of the second switching die; and
cross coupling some of the outputs of the ingress switches of the second switching die to the multiplexers of the first switching die.
16. A configurable cross point switching unit comprising:
a component die including an interconnection interface region including input ports and output ports;
a plurality of switching dies stacked on the component die, each of the plurality of switching dies including a plurality of ingress switches, a plurality of multiplexers and a plurality of middle stage switches, wherein the outputs of the ingress switches are connected via the multiplexers to the inputs of the middle stage switches for each of the plurality of switching dies;
a plurality of input through-silicon vias (TSVs) between the input ports of the interconnection interface region and the inputs of the ingress switches of the plurality of switching dies;
a plurality of output TSVs between the output ports of the interconnection interfaces and the outputs of the ingress switches and the middle stage switches; and
wherein at least one of the switching dies includes a first plurality of TSVs between the outputs of the ingress switches and the multiplexer of a switching die on top of the at least one of the switching dies and a second plurality of TSVs between the outputs of the ingress switches and the multiplexer of a switching die below the at least one of the switching dies.
17. The configurable cross point switching unit of claim 16 , wherein the inputs to the multiplexers are programmed by configuration information generated by FPGA logic of the component die, the configuration information transmitted via interconnections to the multiplexer.
18. The configurable cross point switching unit of claim 16 , further comprising a processor to program the connections to the input of the middle switch via the multiplexer.
19. The configurable cross point switching unit of claim 16 , wherein the multiplexers of the first and second switching dies are configured to select a predetermined number of input ports on the switching interface region as switch inputs and a predetermined number of output ports on the switching interface regions as switch outputs.
20. The configurable cross point switching unit of claim 16 , wherein the multiplexers of the first and second switching dies are configured to create a wide channel bit length port by assigning the multiple inputs of the egress switches of the first and second switching dies to a single input port.