Granted Patent B2

US 12,664,082 · App. 18/987,844 · Granted Jun 23, 2026

Inventors: Sharath Raghava (Los Gatos, CA); Nagabhushan Chitlur (Portland, OR); Harsha Gupta (Sunnyvale, CA)

Assignee: Altera Corporation

G06F12/0238G06F1/30G06F9/30047G06F12/0891G06F12/0895G06F2212/466

Abstract

Claims (63)

1 . A method comprising:

receiving, via a coherent link and at a device of an integrated circuit system, a cache line comprising a destination address, wherein the coherent link includes coherent link soft logic in the device;

determining, via the coherent link soft logic of the device, a type of memory or storage associated with the destination address as persistent or non-persistent; and

tagging, via the coherent link soft logic of the device, the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address, wherein the coherent link soft logic comprises a decoder configured to decode the cache line to determine a destination of the cache line.

2 . The method of claim 1 , comprising:

receiving a power fail signal at the integrated circuit system;

in response to receiving the power fail signal, to the cache line comprising a memory write request, and to the tagging indicating that the type of memory or storage associated with the destination address is persistent, selectively committing the cache line to persistent memory; and

in response to receiving the power fail signal and to the tagging indicating that the type of memory or storage associated with the destination address is non-persistent, selectively refraining from committing the cache line to volatile memory.

3 . The method of claim 1 , comprising, in response to receiving a power fail signal and the cache line comprising a memory read request, dropping the memory read request and returning a response indicative of the dropping.

4 . The method of claim 1 , comprising, in response to receiving a power fail signal and the cache line comprising a storage write request, committing the cache line to storage.

5 . The method of claim 1 , comprising:

in response to determining that the type of memory or storage associated with the destination address is persistent, tagging the cache line with metadata indicative of the cache line being directed to persistent memory;

in response to determining that the type of memory or storage associated with the destination address is non-persistent, refraining from tagging the cache line with the metadata indicative of the cache line being directed to persistent memory; and

processing the cache line based at least in part upon the presence of metadata indicative of the cache line being directed to persistent memory.

6 . The method of claim 1 , comprising processing, via a memory or storage controller, the cache line regardless of what the tag of the cache line indicates.

7 . The method of claim 1 , wherein the device comprises a field programmable gate array (FPGA) device or an application-specific integrated circuit (ASIC) device.

8 . An integrated circuit system comprising:

a central processing unit;

a device comprising:

a memory controller configured to manage memory coupled to the device; and

a decoder configured to decode a cache line to determine a destination of the cache line;

a communication link coupling the device to the central processing unit;

a volatile memory coupled to the device; and

a persistent memory coupled to the device;

wherein the integrated circuit system is configured to:

receive, via a coherent link and at the device of the integrated circuit system, the cache line, wherein the coherent link includes coherent link soft logic in the device;

identify, via the coherent link soft logic of the device, whether the cache line is directed to the persistent memory or the volatile memory; and

tag, via the coherent link soft logic of the device, the cache line with metadata to distinguish cache lines directed to the persistent memory from cache lines directed to the volatile memory, wherein the coherent link soft logic of the device comprises the decoder configured to decode the cache line to determine the destination of the cache line.

9 . The integrated circuit system of claim 8 , wherein the memory controller is configured to:

receive a power fail signal; and

in response to receiving the power fail signal, to the cache line comprising a memory write request, and to the tagging indicating that the cache line is directed to the persistent memory, selectively commit the cache line to the persistent memory; and

in response to receiving the power fail signal and to the tagging indicating that the cache line is directed to non-persistent memory, selectively refrain from committing the cache line to the volatile memory.

10 . The integrated circuit system of claim 9 , comprising a battery backup configured to power the integrated circuit system when the power fail signal is asserted on the integrated circuit system, and wherein the battery backup is configured to support committing persistent cache lines subsequent to the power fail signal.

11 . The integrated circuit system of claim 10 , wherein the battery backup is sized based upon a queue length corresponding to an amount of cache lines to be committed to the persistent memory and not based upon a queue length corresponding to an amount of cache lines to be committed to the volatile memory.

12 . The integrated circuit system of claim 8 , wherein the memory controller is configured to:

receive a power fail signal; and

in response to receiving the power fail signal and the cache line comprising a memory read request, respond to the cache line with a response, wherein the response comprises a default response.

13 . The integrated circuit system of claim 8 , comprising:

a storage coupled to the device;

wherein the device comprises a storage controller configured to manage the storage;

wherein the integrated circuit system is configured to:

receive a second cache line;

identify whether the second cache line is directed to the persistent memory, the volatile memory, or the storage; and

tag, with metadata, the cache line to distinguish cache lines directed to the volatile memory from cache lines directed to the persistent memory.

14 . The integrated circuit system of claim 8 , wherein the device comprises a field programmable gate array (FPGA) device or an application-specific integrated circuit (ASIC) device.

15 . The integrated circuit system of claim 8 , wherein logic on the device is configured to:

receive a second cache line from the central processing unit;

determine if the second cache line is directed to the persistent memory;

in response to determining that the second cache line is directed to the persistent memory, tag the second cache line with metadata to ensure committing of the second cache line to the persistent memory; and

in response to determining that the second cache line is not directed to the persistent memory, drop the second cache line.

16 . The integrated circuit system of claim 8 , wherein the central processing unit is coupled to a second persistent memory and to a second volatile memory, and wherein the central processing unit is configured to tag a second cache line as directed to the second persistent memory or to the second volatile memory to distinguish second cache lines directed to the second persistent memory from second cache lines direct to the second volatile memory.

17 . A non-transitory, tangible, and computer-readable medium comprising instructions that, when executed by a processor of a memory controller, cause the memory controller to perform operations comprising:

receiving, via a coherent link and at a device of an integrated circuit system, a cache line into a queue configured to store pending operations, wherein the coherent link includes coherent link soft logic in the device;

determining, via the coherent link soft logic of the device, if the cache line is directed to persistent memory or non-persistent memory based upon whether the cache line is tagged with metadata, wherein the coherent link soft logic of the device comprises a decoder configured to decode the cache line to determine a destination of the cache line;

identifying a power failure; and

in response to identifying the power failure:

committing the cache line to memory in response to the cache line being directed to the persistent memory; and

refraining from committing the cache line to memory in response to the cache line being directed to the non-persistent memory.

18 . The non-transitory, tangible, and computer-readable medium of claim 17 , wherein the operations comprise, during a time when no power failure is present, committing the cache line to memory regardless of whether the cache line is directed to the persistent memory or the non-persistent memory.

19 . The non-transitory, tangible, and computer-readable medium of claim 17 , wherein the queue comprises a write pending queue.

20 . The non-transitory, tangible, and computer-readable medium of claim 17 , wherein the cache line comprises a memory read request, and wherein the operations comprise:

responding to the cache line with a default response; and

dropping the cache line.

Assignments (1)

Continuity (2)

References Cited (18)