Apparatus and methods of dynamic transmit equalization

1. An integrated circuit comprising:

physical coding sublayer (PCS) circuitry configured to encode data bytes for transmission and decode received data bytes;

physical layer and media access control (PhyMAC) circuitry configured to control link initialization and training;

an interface between the PCS circuitry and the PhyMAC circuitry;

an equalization control circuit, external to the PCS circuitry, wherein the equalization control circuit is operable to perform dynamic transmit equalization using preset data using said interface between the PCS circuitry and the PhyMAC circuitry; and

a preset-to-coefficient converter in the PhyMAC circuitry which is configured to convert transmitter preset data to transmitter coefficient data.

2. The integrated circuit of claim 1 , wherein the equalization control circuit is operable to apply preset data for equalization in an upstream component, and wherein the equalization control circuit is operable to transmit the preset data to a downstream component for application therein.

3. The integrated circuit of claim 1 , wherein the equalization control circuit is operable to refine receiver coefficients at an upstream component.

4. The integrated circuit of claim 1 , wherein the equalization control circuit is operable to refine transmitter coefficients at an upstream component.

5. The integrated circuit of claim 1 , wherein the integrated circuit comprises an upstream component, and wherein the upstream component is operable to receive commands transmitted from a downstream component, check reception of the commands, generate acknowledgment or no acknowledgement responses based on the reception, and transmit the responses to the downstream component.

6. The integrated circuit of claim 1 , wherein the integrated circuit comprises an upstream component, and wherein the upstream component is operable to generate and transmit commands to a downstream component, receive acknowledgment or no acknowledgement responses from the downstream component, and determine a bit error rate based on the responses.

7. The integrated circuit of claim 1 , wherein the integrated circuit comprises a downstream component, and wherein the downstream component is operable to generate and transmit commands to an upstream component, receive acknowledgment or no acknowledgement responses from the upstream component, and determine a bit error rate based on the responses.

8. The integrated circuit of claim 1 , wherein the integrated circuit comprises a downstream component, and wherein the downstream component is operable to receive commands transmitted from an upstream component to the downstream component, check reception of the commands and generate acknowledgment or no acknowledgement responses based on the reception, and transmit the responses to the upstream component.

9. The integrated circuit of claim 1 , further comprising:

a training sequence transmitter in the PhyMAC circuitry which is configured to cause transmission of commands to a training sequence receiver in another integrated circuit.

10. The integrated circuit of claim 1 , further comprising:

a training sequence receiver in the PhyMAC circuitry which is configured to receive responses from a training sequence transmitter in another integrated circuit, wherein the training sequence receiver is operable to determine a bit error rate based on the responses.

11. The integrated circuit of claim 1 , wherein the preset-to-coefficient converter is operable to output the transmitter coefficient data using said interface to the PCS circuitry.

12. The integrated circuit of claim 11 , further comprising:

a look-up-table in the PCS circuitry which is configured to translate the transmitter coefficient data to analog coefficient levels.

13. The integrated circuit of claim 1 , wherein the integrated circuit comprises a field programmable gate array.

14. The integrated circuit of claim 1 , wherein the equalization control circuit and the PhyMAC circuitry comprise programmable logic which is configured to perform the dynamic transmit equalization using said interface between the PCS circuitry and the PhyMAC circuitry.

15. A method of dynamic transmit equalization, the method comprising:

encoding data bytes for transmission and decode received data bytes using physical coding sublayer (PCS) circuitry;

controlling link initialization and training using physical layer and media access control (PhyMAC) circuitry;

performing dynamic transmit equalization using preset data by an equalization control circuit external to the PCS circuitry using an interface between the PCS circuitry and the PhyMAC circuitry;

applying default settings for equalization in an upstream component using a preset-to-coefficient converter in the PhyMAC circuitry to convert transmitter preset data to transmitter coefficient data;

transmitting said default settings for equalization to a downstream component for application therein;

refining receiver coefficients at the upstream component; and

refining transmitter coefficients at the upstream component.

16. The method of claim 15 , further comprising:

receiving commands transmitted from the downstream component to the upstream component;

checking reception of the commands and generating acknowledgment or no acknowledgement responses based on the reception; and

transmitting the responses to the downstream component.

17. The method of claim 16 , wherein the refining of transmitter coefficients at the upstream component comprises:

generating and transmitting commands to the downstream component;

receiving acknowledgment or no acknowledgement responses from the downstream component; and

determining a bit error rate based on the responses.

18. The method of claim 15 further comprising:

receiving default settings for equalization from an upstream component;

applying the default settings for equalization in the downstream component;

refining transmitter coefficients at the downstream component; and

refining receiver coefficients at the downstream component.

19. The method of claim 18 , further comprising:

generating and transmitting commands to an upstream component;

receiving acknowledgment or no acknowledgement responses from the upstream component; and

determining a bit error rate based on the responses.

20. The method of claim 18 , further comprising:

receiving commands transmitted from the upstream component to the downstream component;

checking reception of the commands and generating acknowledgment or no acknowledgement responses based on the reception; and

transmitting the responses to the upstream component.

21. A transceiver circuit with dynamic transmit equalization, the transceiver circuit comprising:

physical coding sublayer (PCS) circuitry;

physical layer and media access control (PhyMAC) circuitry;

a preset-to-coefficient converter in the PhyMAC circuitry which is configured to convert transmitter preset data to transmitter coefficient data;

an interface between the PCS circuitry and the circuitry; and

an equalization controller which is external to the PCS circuitry and which is configured to perform dynamic transmit equalization using preset data using said interface,

wherein the interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the PhyMAC circuitry to the PCS circuitry.

22. The transceiver circuit of claim 21 , wherein the PhyMAC circuitry comprises:

a training sequence transmitter configured to cause transmission of commands to a training sequence receiver in another transceiver circuit; and

a training sequence receiver configured to receive responses from a training sequence receiver in the another transceiver circuit and to determine a bit error rate based on the responses.

23. The transceiver circuit of claim 21 , wherein the equalization controller comprises programmable logic configured to perform dynamic transmit equalization using said interface between the PCS circuitry and the PhyMAC circuitry.

24. The transceiver circuit of claim 21 , wherein the PhyMAC circuitry comprises programmable logic configured to cause transmission of commands to a training sequence receiver in another transceiver circuit, receive responses from the training sequence receiver in the other transceiver circuit, and determine a bit error rate based on the responses.