Programmable logic device with integrated network-on-chip

1. A programmable integrated circuit comprising a plurality of Network-On-Chip (NoC) stations, wherein a first NoC station in the plurality of NoC stations receives a first clock input and comprises:

a first hard-IP interface comprising:

a first bidirectional connection that communicatively couples the first NoC station to a local logic area of the programmable integrated circuit; and

a second bidirectional connection that communicatively couples the first NoC station to a second NoC station in the plurality of NoC stations neighboring the first NoC station; and

a user-programmable first soft-IP interface that supports the first hard-IP interface and comprises Quality-of-Service (QoS) circuitry that provides functionality to the first NoC station based at least in part on a QoS parameter instantiated in the first soft-IP interface, wherein, when the QoS parameter comprises a data width of the first NoC station, the functionality comprises:

segmenting data received at the first NoC station with a width greater than the data width into smaller data units to facilitate processing by the first NoC station; and

padding data received at the first NoC station with a width less than the data width into a padded data unit to facilitate processing by the first NoC station.

2. The programmable integrated circuit of claim 1 , wherein:

the first soft-IP interface is instantiated via a software library function;

the software library function specifies the QoS parameter; and

the software library function provides Register-transfer-level (RTL) code used to interface the first soft-IP interface with the first hard-IP interface.

3. The programmable integrated circuit of claim 1 , wherein the plurality of NoC stations form a backbone routing network logically separated from other logic of the programmable integrated circuit.

4. The programmable integrated circuit of claim 1 , wherein the QoS parameter comprises a bit rate, a latency, a delay, a jitter, a packet dropping probability, a data disposability, a data priority, a bit error rate, a buffer size, a store-and-forward policy, or any combination thereof.

5. The programmable integrated circuit of claim 1 , wherein a third NoC station in the plurality of NoC stations comprises:

a second hard-IP interface comprising a unidirectional connection that communicatively couples the third NoC station to a fourth NoC station in the plurality of NoC stations neighboring the third NoC station; and

a user-programmable second soft-IP interface that supports the second hard-IP interface.

6. The programmable integrated circuit of claim 1 , wherein the first clock input comprises a higher frequency than a second clock input provided to the local logic area of the programmable integrated circuit.

7. An integrated circuit comprising a Network-On-Chip (NoC) station that facilitates data communication in the integrated circuit, wherein the NoC station comprises:

a hard-IP interface that communicatively couples the NoC station to a logic area of the integrated circuit, one or more neighboring NoC stations, or both; and

a user-programmable soft-IP interface that, based at least in part on a first QoS parameter comprising data width of the NoC station:

segments first data received by the NoC station via the hard-IP interface into smaller data units to facilitate processing by the NoC station when width of the first data is greater than the data width; and

pads second data received by the NoC station via the hard-IP interface to generate a padded data unit to facilitate processing by the NoC station when width of the second data is less than the data width.

8. The integrated circuit of claim 7 , wherein:

the soft-IP interface is instantiated via a software library function;

the software library function specifies the first QoS parameter; and

the software library function provides Register-transfer-level (RTL) code used to interface the soft-IP interface with the hard-IP interface.

9. The integrated circuit of claim 8 , wherein the soft-IP interface supports the hard-IP interface based at least in part on a second QoS parameter comprising a bit rate, a latency, a delay, a jitter, a packet dropping probability, a data disposability, a data priority, a bit error rate, a buffer size, a store-and-forward policy, or any combination thereof.

10. The integrated circuit of claim 7 , wherein the soft-IP interface controls flow of data streams to or from the NoC station by multiplexing the data streams, interleaving the data streams, or both based at least in part on a second QoS parameter comprising an available bandwidth parameter.

11. The integrated circuit of claim 7 , wherein the data width comprises a data-only setting or a data-plus-metadata setting.

12. The integrated circuit of claim 7 , wherein:

the NoC station comprises a buffer memory that stores data during a network busy condition; and

the soft-IP interface sets size of the buffer memory based at least in part on a second QoS parameter.

13. A method for configuring a Network-On-Chip (NoC) station of an integrated circuit comprising a hard-IP interface and a soft-IP interface that supports the hard-IP interface, comprising:

instantiating, via a software library function, the soft-IP interface;

specifying, via the software library function, at least one Quality-of-Service (QoS) parameter of the NoC station to the soft-IP interface;

outputting, via the software library function, Register-transfer-level (RTL) used to interface the soft-IP interface and the hard-IP interface; and

instructing, via the software library function, the soft-IP interface to configure based on the at least one QoS parameter to provide the NoC station functionality not otherwise provided by the hard-IP interface.

14. The method of claim 13 , wherein the software library function comprises a MegaFunction.

15. The method of claim 13 , wherein:

the at least one QoS parameter comprises a buffer size parameter; and

instructing the soft-IP interface to configured comprises instructing the soft-IP interface to adjust size of a buffer memory of the NoC station based at least in part on the buffer size parameter.

16. The method of claim 13 , wherein:

the at least one QoS parameter comprises an available bandwidth parameter; and

the functionality comprises regulating streams of data to or from the NoC station based at least in part on the available bandwidth parameter.

17. The method of claim 16 , wherein regulating the streams of data comprises multiplexing the streams of data, interleaving the streams of data, or both.

18. The method of claim 13 , wherein the one or more QoS parameters comprise a bit rate, a latency, a delay, a jitter, a packet dropping probability, a data disposability, a data priority, a bit error rate, a buffer size, a store-and-forward policy, or any combination thereof.

19. The method of claim 13 , wherein the software library function comprises a user interface, software, a supporting implementation, or any combination thereof.

20. A method for configuring a Network-On-Chip (NoC) station of an integrated circuit comprising a hard-IP interface and a soft-IP interface that supports the hard-IP interface, comprising:

instantiating, via a software library function, the soft-IP interface;

specifying, via the software library function, at least one Quality-of-Service (QoS) parameter of the NoC station to the soft-IP interface, wherein the at least one QoS parameter comprises a data width of the NoC station; and

instructing, via the software library function, the soft-IP interface to configure based on the at least one QoS parameter to provide the NoC station functionality not otherwise provided by the hard-IP interface, wherein the functionality comprises:

segmenting data received at the NoC station of a width greater than the data width into smaller data units to facilitate processing by the NoC station; and

padding data received at the NoC station of a width less than the data width into a padded data unit to facilitate processing by the NoC station.