Embedded memory blocks with adjustable memory boundaries

1. An integrated circuit, comprising:

a memory block that is partitioned into first and second memory block portions, wherein the first memory block portion includes memory elements of a first memory type, wherein the second memory block portion includes memory elements of a second memory type, and wherein the memory elements of the first type comprise configuration flash memory that stores configuration bits; and

a control circuit that receives configuration data, wherein the configuration data includes memory partitioning information for repartitioning the memory elements of the first and second types in the memory block into first and second repartitioned memory block portions.

2. The integrated circuit defined in claim 1 , wherein the memory partitioning information includes information on the amount of unused memory in the first memory block portion that is derived from the first memory block portion during a design compilation operation of the integrated circuit.

3. The integrated circuit defined in claim 2 , wherein the unused memory of the first memory block portion is allocated to the second memory block portion.

4. The integrated circuit defined in claim 3 , wherein the first repartitioned memory includes the first memory block portion minus the unused memory, and wherein the second repartitioned memory block portion includes the second memory block portion and the unused memory.

5. The integrated circuit defined in claim 4 , wherein the memory partitioning information further includes a memory partitioning constraint for the second repartitioned memory block portion, and wherein the memory partitioning constraint specifies a start address for the second repartitioned memory block portion.

6. The integrated circuit defined in claim 5 , wherein the memory partitioning constraint further includes at least one memory segment to be partitioned in the second repartitioned memory block portion.

7. The integrated circuit defined in claim 6 , wherein the at least one memory segment is assigned a memory segment address range based on the start address of the second repartitioned memory block portion.

8. The integrated circuit defined in claim 6 , further comprising:

a storage circuit that stores memory address data associated with the first repartitioned memory block portion and the second repartitioned memory block portion, including the at least one memory segment to be partitioned in the second repartitioned memory block portion.

9. The integrated circuit defined in claim 1 , wherein the memory elements of the second type comprise user flash memory for storing user data.

10. A method for using a computer-aided design tool implemented on computing equipment to configure an integrated circuit device having a memory block that is divided into a first memory block portion and a second memory block portion, the method comprising:

with the computer-aided design tool, generating configuration data for the integrated circuit device and compressing the configuration data, wherein the first memory block portion is used to store the compressed configuration data;

with the computer-aided design tool, determining whether unused memory is present in the first memory block portion by analyzing the compressed configuration data; and

in response to determining that the unused memory is present in the first memory block portion, adjusting the size of the first memory block portion and the size of the second memory block portion.

11. The method defined in claim 10 , wherein adjusting the size of each of the first and second memory block portions comprises allocating the unused memory of the first memory block portion to the second memory block portion.

12. The method defined in claim 11 , further comprising:

with the computer-aided design tool, receiving a user input that specifies a memory partition constraint for the second memory block portion, wherein the memory partition constraint includes a start address for the second memory block portion and at least one memory segment for the second memory block portion.

13. The method defined in claim 12 further comprising:

with the computer-aided design tool, determining whether the memory partition constraint for the second memory block portion meets a predetermined memory size requirement of the first and second memory block portions.

14. A method for configuring an integrated circuit, comprising:

receiving custom logic design data for the integrated circuit having a memory block that is partitioned into a first portion of a first memory type and a second portion of a second memory type that is different than the first memory type;

determining an amount of unused memory in the first portion of the first memory type by analyzing the custom logic design data; and

in response to determining that the amount of unused memory exceeds a predetermined threshold, repartitioning the memory block into a first repartitioned portion of the first memory type and a second repartitioned portion of the second memory type, wherein the predetermined threshold is a fraction of the memory block.

15. The method defined in claim 14 , wherein the repartitioning comprises allocating the first portion of the first memory type without the unused memory into the first repartitioned portion of the first memory type, wherein the first repartitioned portion of the first memory type is used to store static configuration data, and wherein the second repartitioned portion of the second memory type is used to store user data.

16. The method defined in claim 15 , wherein the repartitioning further comprises allocating the second portion of the second memory type and the unused memory of the first portion of the first memory type into the second repartitioned portion of the second memory type.

17. The method defined in claim 16 , further comprising:

receiving a user input from a user interface, wherein the user input includes a memory partition constraint for the second repartitioned portion of the second memory type.

18. The method defined in claim 17 , wherein the memory partition constraint includes a number of memory partitions having a size, the method further comprising:

determining whether the size of the number of memory partitions meets a predetermined memory size requirement of the memory block.

19. The method defined in claim 18 , further comprising:

partitioning the second repartitioned portion of the second memory type into at least one partitioned segment based on the memory partition constraint in response to determining that the size of the number of memory partitions meets the predetermined memory size requirement of the memory block.

20. The method defined in claim 19 , wherein the memory partition constraint further includes an entry point address for the second repartitioned portion of the second memory type, and wherein the method comprises assigning a segment address range for the at least one partitioned segment based on the entry point address of the second repartitioned portion of the second memory type.