Method and apparatus for implementing a system-level design tool for design planning and architecture exploration
View Patent ↗A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
1. A method for designing a system on a target device:
mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system; and
generating a visual representation of the mapping.
2. The method of claim 1 , wherein the mapping of the high-level description accounts for wire use of the system and wire resources on the target device.
3. The method of claim 1 , wherein the mapping of the high-level description accounts for timing requirements of the system and routing congestion.
4. The method of claim 1 , wherein the high-level description comprises identities of components in the system and resource usage of the components.
5. The method of claim 1 , wherein the high-level description comprises width and speed requirement of data paths between components in the system.
6. The method of claim 1 , wherein the high-level description comprises system-level meta-data describing latency tolerances of data paths between components in the system and uses of the data paths.
7. The method of claim 1 , wherein the high-level description comprises block-level meta-data describing a component's routing porosity and maximum frequency.
8. The method of claim 1 , further comprising mapping modifications to the high-level of the description onto the target device.
9. The method of claim 1 , further comprising:
mapping the high-level of the description of the system onto a different model of the target device prior to generating the RTL of the system; and
generating a visual representation of the mapping onto the different model of the target to the user.
10. The method of claim 1 , further comprising performing latency planning.
11. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:
generating a plurality of models of a target device from a description input by a user;
mapping a high-level description of a system onto the models of the target device, wherein the high-level description of the system is at a level higher than a register transfer level description; and
generating a visual representation of the mappings.
12. The non-transitory computer readable medium of claim 11 , wherein the description input by the user comprises one or more physical floor plan descriptions of the target device.
13. The non-transitory computer readable medium of claim 11 , wherein the description input by the user comprises a description of a range of global routing resources.
14. The non-transitory computer readable medium of claim 11 , wherein the description input by the user comprises delay metrics associated with pipelining data paths and widening data paths.
15. The non-transitory computer readable medium of claim 11 , wherein the description input by the user describes a range of wire-widths available on the target device.
16. The non-transitory computer readable medium of claim 11 , wherein the high-level description of the system is at a level higher than a register transfer level description.
17. The non-transitory computer readable medium of claim 11 , wherein the visual representation of the mapping comprises a slicing floor plan.
18. The non-transitory computer readable medium of claim 11 , wherein the visual representation of the mapping comprises a mapped view illustrating resource use.
19. The non-transitory computer readable medium of claim 11 , wherein the method further comprises:
modifying one of the models of the target device; and
mapping the high-level description of the system onto the modified model.
20. The non-transitory computer readable medium of claim 11 , wherein the method further comprises performing latency planning comprises by:
determining whether bandwidth requirements are satisfied; and
modifying one of the plurality of models to increase bandwidth support in response to determining that the bandwidth requirements are not satisfied.
21. The non-transitory computer readable medium of claim 11 , wherein the method further comprises performing latency planning comprises by:
determining whether a latency constraint is satisfied; and
modifying one of the plurality of models in response to determining that the latency constraint is not satisfied.
22. A system designer, comprising:
a mapping unit that maps a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system; and
a mapping description unit that generates a visual representation of the mapping, wherein at least one of the mapping unit and the mapping description unit is implemented by a processor.
23. The system designer of claim 22 further comprising a target device modeling unit that generates the model of the target device from a description input by a user.
24. The system designer of claim 22 , wherein the mapping unit maps the high-level of the description of the system onto a different model of the target device.
25. The system designer of claim 22 , wherein the mapping unit that maps modifications to the high-level of the description onto the model of the target device.