Incremental register retiming of an integrated circuit design
View Patent ↗A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.
1. A method for operating circuit design computing equipment, comprising:
with the circuit design computing equipment, receiving a first circuit design and a first circuit design implementation that is at least partially generated as a result of a register retiming operation on the first circuit design;
with the circuit design computing equipment, receiving a second circuit design that is the result of an engineering-change-order of the first circuit design;
with the circuit design computing equipment, identifying differences between the first circuit design and the second circuit design;
with the circuit design computing equipment, performing a compilation of the second circuit design to generate a second circuit design implementation, wherein the compilation involves performing an incremental register retiming operation that is based on the identified differences between the first and second circuit designs and the first circuit design implementation, and wherein performing the incremental register retiming operation comprises:
moving a register across a combinational node within the second circuit design; and
generating configuration data for configuring an integrated circuit based on the second circuit design implementation.
2. The method of claim 1 , wherein identifying differences between the first circuit design and the second circuit design comprises:
identifying a first region of the first circuit design that has a predetermined functionality; and
identifying a second region of the second circuit design that has the same predetermined functionality.
3. The method of claim 2 , further comprising:
identifying a third region of the first circuit design that is coupled to the first region; and
identifying a fourth region of the second circuit design that is coupled to the second region.
4. The method of claim 3 , wherein performing the incremental register retiming operation further comprises:
moving registers between the fourth region and a sub-region of the first region.
5. The method of claim 3 , wherein moving the register across the combinational node within the second circuit design comprises:
moving the register across the combinational node within the fourth region.
6. The method of claim 5 , wherein moving the register across the combinational node further comprises:
enabling a first register in a first routing resource that is connected to the combinational node; and
disabling a second register in a second routing resource that is connected to the combinational node and that is different from the first routing resource.
7. The method of claim 3 , wherein performing the compilation further comprises:
preserving a portion of the first circuit design implementation, wherein the portion implements at least a sub-region of the first region in the second circuit design implementation.
8. The method of claim 7 , wherein performing the incremental register retiming operation further comprises:
preserving timing constraints in the portion of the first circuit design implementation.
9. The method of claim 8 , further comprising:
generating additional timing constraints in the fourth region.
10. The method of claim 2 , wherein performing the compilation further comprises:
preserving a portion of the first circuit design implementation, wherein the portion implements at least a sub-region of the first region in the second circuit design implementation, and wherein performing the incremental register retiming operation further comprises:
preserving timing constraints in the portion of the first circuit design implementation.
11. The method defined in claim 1 , wherein performing the incremental register retiming operation comprises:
incrementally updating a dependency graph associated with the second circuit design.
12. The method defined in claim 11 , wherein performing the incremental register retiming operation further comprises:
incrementally updating a constraint graph associated with the second circuit design.
13. The method defined in claim 1 , wherein performing the incremental register retiming operation comprises:
incrementally updating a constraint graph associated with the second circuit design.