Systems and methods for configuring an SOPC without a need to use an external memory
Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.
1. An integrated circuit device comprising:
field programmable gate array (FPGA) fabric; and
a communication interface;
wherein:
during a first initialization stage, the integrated circuit device configures the communication interface to enable communication via the communication interface; and
during a second initialization stage, the integrated circuit device initially configures at least a portion of the FPGA fabric using data received via the communication interface.
2. The integrated circuit of claim 1 , wherein, during a third initialization stage, in response to the integrated circuit initially configuring at least the portion of the FPGA fabric, the integrated circuit configures the communication interface to operate in a user mode.
3. The integrated circuit of claim 1 , wherein, during the first initialization stage, the integrated circuit configures the communication interface using interface configuration data received from a programmable read-only memory (PROM).
4. The integrated circuit of claim 1 , wherein the integrated circuit configures the communication interface to enable communication using a peripheral component interconnect express (PCI-e) standard.
5. The integrated circuit of claim 1 , wherein the portion of the FPGA fabric does not include the communication interface.
6. The integrated circuit of claim 1 , wherein the data is received from a data source external to the integrated circuit.
7. A system comprising:
an integrated circuit comprising:
field programmable gate array (FPGA) fabric; and
a communication interface;
wherein:
during a first initialization stage, the integrated circuit configures the communication interface to enable communication via the communication interface; and
during a second initialization stage, the integrated circuit initially configures at least a portion of the FPGA fabric using data received via the communication interface.
8. The system of claim 7 , wherein during the first initialization stage, the integrated circuit configures the communication interface to enable communication via a link between the communication interface and a data source.
9. The system of claim 8 , wherein the data is received by the communication interface from the data source over the link.
10. The system of claim 8 , wherein the data source comprises a host computer or processor.
11. An integrated circuit comprising:
field programmable gate array (FPGA) fabric; and
a communication interface, wherein:
before a first initialization stage, the communication interface is not configured to enable the communication interface to receive data via a first communication protocol;
during the first initialization stage, the communication interface is adapted to become configured to enable the communication interface to receive data via the first communication protocol; and
during a second initialization stage, the communication interface is adapted to receive data via the first communication protocol to enable the integrated circuit device to initially configure at least a portion of the FPGA fabric.
12. The integrated circuit of claim 11 , wherein, during a third initialization stage, in response to the integrated circuit initially configuring at least the portion of the FPGA fabric, the communication interface is adapted to become configured to operate in a user mode.
13. The integrated circuit of claim 11 , wherein, during the first initialization stage, the integrated circuit is adapted to configure the communication interface using interface configuration data received from a programmable read-only memory (PROM).
14. One or more tangible, non-transitory, machine-readable media comprising instructions configured to cause a control block of an integrated circuit to:
during a first initialization stage, configure a communication interface of the integrated circuit, wherein the configuration of the communication interface during the first initialization stage enables communication via the communication interface; and
during a second initialization stage, initially configure at least a portion of field programmable gate array (FPGA) fabric using data received via the communication interface.
15. The one or more machine-readable media of claim 14 , comprising instructions configured to cause the control block to, during a third initialization stage, in response to the control block initially configuring at least the portion of the FPGA fabric, configure the communication interface to operate in a user mode.
16. The one or more machine-readable media of claim 14 , wherein, during the first initialization stage, the control block configures the communication interface using interface configuration data received from a programmable read-only memory (PROM).
17. The one or more machine-readable media of claim 14 , wherein the control block configures the communication interface to enable communication using a peripheral component interconnect express (PCI-e) standard.
18. A method comprising:
during a first initialization stage, configuring, via a control block of an integrated circuit, a communication interface of the integrated circuit, wherein the configuration of the communication interface during the first initialization stage enables communication via the communication interface; and
during a second initialization stage, initially configuring, via the control block, at least a portion of field programmable gate array (FPGA) fabric using data received via the communication interface.
19. The method of claim 18 , wherein the portion of the FPGA fabric does not include the communication interface.
20. The method of claim 18 , comprising receiving, via the control block, the data from a data source external to the integrated circuit.