Network-on-chip (NOC) with flexible data width
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
1. An integrated circuit comprising:
a first programmable logic circuit;
a second programmable logic circuit; and
a network-on-chip (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC comprises:
a plurality of data paths that collectively have the configurable data width; and
a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
receives a first packet from the first programmable logic circuit, wherein the first packet comprises a destination identifier;
performs a first lookup operation in a table based on the destination identifier; and
transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation.
2. The integrated circuit of claim 1 , wherein a route used to transmit the first packet via the NoC is programmable.
3. The integrated circuit of claim 1 , comprising a network-on-chip (NoC) access circuit between the NoC and the first programmable logic circuit.
4. The integrated circuit of claim 3 , wherein the NoC access circuit transmits chopped data associated with the first packet to the NoC.
5. The integrated circuit of claim 3 , wherein the NoC access circuit controls ingress based on quality of service (QoS) settings.
6. The integrated circuit of claim 1 , wherein the configurable data width of the NoC is configurable into one of a plurality of data widths.
7. The integrated circuit of claim 6 , wherein the plurality of data widths includes a first data width and a second data width, wherein the plurality of data paths collectively have:
at a first time, the first data width between the first programmable logic circuit and the second programmable logic circuit; and
at a second time, the second data width between the first programmable logic circuit and the second programmable logic circuit.
8. The integrated circuit of claim 1 , comprising circuitry that receives the first packet at egress from the NoC.
9. The integrated circuit of claim 1 , wherein the NoC is configurable to transmit the first packet to a memory outside a programmable logic area.
10. The integrated circuit of claim 1 , wherein the first lookup operation identifies an output from the first packet switch that determines where the first packet is sent.
11. The integrated circuit of claim 1 , wherein the NoC is configurable to implement the configurable data width based on a parameter.
12. The An integrated circuit comprising:
a first programmable logic circuit;
a second programmable logic circuit;
a network-on-chip (NoC) access circuit that receives a first packet from the first programmable logic circuit, wherein the first packet comprises a destination identifier;
a network-on-chip (NoC) egress circuit; and
a network-on-chip (NoC) coupled to the first programmable logic circuit via the NoC access circuit and coupled to the second programmable logic circuit via the NoC egress circuit, wherein the NoC is configurable to transmit data based on a data width of a plurality of data widths based on a parameter, wherein the NoC is programmable to transmit the data via any of a plurality of routes, and wherein the NoC comprises:
a plurality of data paths that collectively have the data width of the plurality of data widths; and
a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
receives the first packet from the first programmable logic circuit;
performs a first lookup operation in a table based on the destination identifier; and
transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation.
13. The integrated circuit of claim 12 , wherein the NoC access circuit transmits chopped data associated with the first packet to the NoC.
14. The integrated circuit of claim 13 , wherein the NoC access circuit controls ingress of the chopped data based on QoS settings.
15. The integrated circuit of claim 12 , wherein the NoC is configurable to transmit the first packet to a memory outside a programmable logic area.
16. A system comprising:
a programmable logic device comprising:
a first programmable logic circuit;
a second programmable logic circuit; and
a network-on-chip (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC comprises:
a plurality of data paths associated with the configurable data width; and
a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
receives a first packet, wherein the first packet comprises a destination identifier associated with the first programmable logic circuit;
performs a first lookup operation in a table based on the destination identifier; and
transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation; and
a memory that stores the first packet, wherein the memory is configurable to send the first packet as a transaction from the memory to the first programmable logic circuit; and
an interfacing block that couples the programmable logic device to the memory.
17. The system of claim 16 , comprising a computer readable medium storing instructions that, when executed by a processor, cause a computing system to:
generate a configuration to program the NoC to transmit the first packet from the memory to the first programmable logic circuit; and
store the configuration to program the NoC.
18. The system of claim 16 , wherein a route used to transmit data via the NoC is programmable.
19. The system of claim 16 , comprising a network-on-chip (NoC) access circuit between the NoC and the first programmable logic circuit.
20. The system of claim 19 , wherein the NoC access circuit transmits chopped data associated with the first packet to the NoC.