Hybrid programmable many-core device with on-chip interconnect
View Patent ↗The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.
1. A hybrid programmable logic device, comprising:
programmable logic elements, at least some of which provide at least one hardware acceleration function;
processors interleaved with the programmable logic elements and physically sized such that one physical dimension of each of the processors is equal to a multiple of a same physical dimension of the programmable logic elements; and
first intersecting horizontal and vertical connectors that provide data to and from the programmable logic elements, the processors or any combination therein;
wherein the vertical pitch of the intersecting horizontal and vertical connectors is a multiple of a vertical pitch of at least one of the programmable logic elements of the processors.
2. The device of claim 1 , wherein each of the processors consists of fixed logic elements.
3. The device of claim 1 , wherein the first horizontal and vertical connectors are in a first metal layer of a wiring of the hybrid programmable logic device.
4. The device of claim 1 , wherein the processors are arranged in one of columns or rows.
5. The device of claim 1 , wherein the physical dimension is one of length, width, or height.
6. The device of claim 1 , wherein the first horizontal and vertical connectors are addressable as a homogeneous routing fabric to provide data to and from the processors and programmable logic elements.
7. The device of claim 1 , wherein the first horizontal and vertical connectors only provide data to and from the processors and programmable logic elements.
8. The device of claim 7 , further comprising an ingress/egress processing block that receive data packets and route them to the first horizontal and vertical connectors.
9. The device of claim 8 , further comprising an external memory configured directly connected to the hybrid programmable logic device, wherein the external memory buffers the received data packets.
10. The device of claim 8 , further comprising a network on chip bus, operable only to carry the data packets to and from the ingress/egress processing block.
11. The device of claim 8 , wherein the ingress/egress processing block consists of at least one of a dedicated application-specific integrated circuit (ASIC), or a group of the programmable logic elements.
12. The device of claim 3 , further comprising a second metal layer containing the programmable logic elements and processors.
13. The device of claim 1 , wherein the programmable logic elements change the at least one hardware acceleration function.
14. A hybrid programmable logic device, comprising:
programmable logic elements arranged in tiles that operate at a first clock speed, wherein at least some of the programmable logic elements provide at least one hardware acceleration function;
processors arranged in columns and interleaved with the programmable logic elements that operate at a second clock speed asynchronous with respect to the first clock speed, wherein each of the processors consists of fixed logic elements;
intersecting horizontal and vertical connectors that provide data between the programmable logic elements and processors; and
scheduling circuitry that transmits data on the horizontal and vertical connectors between the programmable logic elements and processors at a rate asynchronous with respect to the second clock speed.
15. The device of claim 14 , wherein the scheduling circuitry receives interrupt messages addressed to at least one of the processors.
16. The device of claim 14 , where a group of the processors comprises circuitry that processes data transmitted between the programmable logic elements and processors to:
identify which of the processors to send the data; and
distribute the data to the identified processors.
17. The device of claim 14 , wherein the scheduling circuitry further comprises a program instruction memory that contains a program instruction set that:
detects a new mode of operation for a group of the processors;
in response to the detection of a new mode of operation, halts operation of the processors in the group;
receives data from the programmable logic elements; and
stores instructions in the program instruction memory based on the received data.
18. A method of initializing and operating a hybrid programmable logic device comprising processors interleaved with programmable logic elements, the method comprising:
computing at least two partitions of the hybrid programmable logic device, wherein each partition comprises a subset of the processors and the programmable logic elements, wherein at least some of the programmable logic elements are programmable to provide at least one hardware acceleration function;
computing at least one measure of processor demand for each of the at least two partitions; and
based on the computed measure of processor demand, altering the power state of the processors and programmable logic elements in at least one of the at least two partitions;
wherein the programmable logic device, the programmable logic elements or any combination thereof exchange data with intersecting horizontal and vertical connectors.
19. The method of claim 18 , wherein altering the power state of the processors and programmable logic devices consists of one of disabling clock circuitry associated with the processors and programmable logic elements, or powering down the processors and programmable logic circuits.
20. The method of claim 18 , wherein computing the measure of processor demand further comprises:
computing a number of received data packets designated for the processors in each of the partitions of the hybrid programmable logic device; and
determining whether the number of received data packets is below a predetermined threshold.
21. The method of claim 18 , wherein computing measure of processor demand further comprises
determining that data packets have not been received by the processors in a partition of the hybrid programmable logic device for a predetermined period of time.
22. The method of claim 18 , wherein computing at least two partitions of the hybrid programmable logic device comprise:
determining hardware acceleration functions used by the processors; and
based on the determination, generating a partition that includes the processors and programmable logic elements associated with the hardware acceleration functions.