Clock management block
View Patent ↗A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.
1. An integrated circuit (IC) comprising:
a plurality of clock sources;
a plurality of clock domains, wherein each clock domain of the plurality of clock domains comprises:
a clock signal that is configurably selected from the plurality of clock sources;
a clock management block (CMB) for providing a control signal that is synchronized with the clock signal;
a first physical distribution network for distributing the clock signal within the clock domain; and
a second physical distribution network for distributing the control signal within the clock domain; and
a plurality of configurable circuits, wherein each of the plurality of configurable circuits is configurable to operate in one of the plurality of clock domains by using a distributed control signal and a distributed clock signal of the one of the plurality of clock domains.
2. The IC of claim 1 , wherein the plurality of clock sources comprise a first clock source and a second clock source, wherein the plurality of clock domains comprise a first clock domain, a second clock domain and a third clock domain, wherein the first clock domain and the second clock domain are configured to route from the first clock source and the third clock domain is configured to route from the second clock source.
3. The IC of claim 2 , wherein the first clock source and the second clock source have different frequencies.
4. The IC of claim 2 , wherein the first clock source and the second clock source have a same frequency but at different phases.
5. The IC of claim 2 , wherein the first clock source and the second clock source are different outputs of a same phase lock loop (PLL).
6. The IC of claim 2 , wherein the second clock source is a divided clock based on the first clock source.
7. The IC of claim 2 , wherein a first configurable circuit configured to operate in the first clock domain and a second configurable circuit configured to operate in the second clock domain are configured to be in a same functional module.
8. The IC of claim 1 further comprising a plurality of clock regions, each clock region comprising a subset of the plurality of clock domains and a subset of the plurality of configurable circuits, wherein each particular configurable circuit in a clock region selectively operates in one of the subset of the plurality of clock domains in the clock region.
9. The IC of claim 8 , wherein one or more of the plurality of clock sources are regional clock sources, wherein a clock source is a regional clock source when only clock domains of one clock region can configurably select the regional clock source.
10. The IC of claim 9 , wherein one or more of the plurality of clock sources are global clock sources, wherein a clock source is a global clock source when clock domains in different clock regions can configurably select the global clock source.
11. An electronic device comprising:
an oscillatory circuit for providing a reference clock;
an integrated circuit (IC) comprising:
a plurality of clock sources, wherein at least one of the plurality of clock sources is based on the reference clock;
a plurality of clock domains, wherein each clock domain of the plurality of clock domains comprises:
a clock signal that is configurably selected from the plurality of clock sources;
a clock management block (CMB) for providing a control signal that is synchronized with the clock signal;
a first physical distribution network for distributing the clock signal within the clock domain; and
a second physical distribution network for distributing the control signal within the clock domain; and
a plurality of configurable circuits, wherein each of the plurality of configurable circuits is configurable to operate in one of the plurality of clock domains by using a distributed control signal and a distributed clock signal of the one of the plurality of clock domains.
12. The electronic device of claim 11 , wherein the plurality of clock sources comprise a first clock source and a second clock source, wherein the plurality of clock domains comprise a first clock domain, a second clock domain and a third clock domain, wherein the first clock domain and the second clock domain are configured to route from the first clock source and the third clock domain is configured to route from the second clock source.
13. For an integrated circuit (IC) comprising a plurality of configurable circuits and a plurality of clock sources, a method comprising:
configuring a particular clock domain by configurably selecting a clock signal from the plurality of clock sources, the particular clock domain comprising (i) a clock management block (CMB) for providing a control signal that is synchronized with the clock signal, (ii) a first physical distribution network for distributing the clock signal within the particular clock domain, and (iii) a second physical distribution network for distributing the control signal within the particular clock domain; and
configuring a plurality of configurable circuits to operate in the particular clock domain, wherein each of the plurality of configurable circuits uses the distributed control signal and the distributed clock signal of the particular clock domain.
14. The electronic device of claim 12 , wherein the first clock source and the second clock source have different frequencies.
15. The electronic device of claim 12 , wherein the first clock source and the second clock source have a same frequency but at different phases.
16. The electronic device of claim 12 , wherein the first clock source and the second clock source are different outputs of a same phase lock loop (PLL).
17. The IC of claim 1 , wherein the control signal controls operations of the configurable circuits in the one of the plurality of clock domains.
18. The IC of claim 1 , wherein the control signal is a reset signal for resetting the configurable circuits in the one of the plurality of clock domains.
19. The IC of claim 1 , wherein the control signal is an enable signal for halting or enabling operations of the configurable circuits in the one of the plurality of clock domains.