Programmable device configuration methods adapted to account for retiming
View Patent ↗A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify critical and near-critical cyclic logic paths within the user logic design, applying timing optimizations to the critical and near-critical cyclic logic paths, and retiming logic paths other than the critical and near-critical cyclic logic paths.
1. A method of configuring an integrated circuit device with a user logic design, said method comprising:
analyzing said user logic design to identify critical and near-critical cyclic logic paths within said user logic design;
applying timing optimizations other than retiming to said critical and near-critical cyclic logic paths; and
retiming logic paths without retiming said critical and near-critical cyclic logic paths.
2. The method of claim 1 wherein said integrated circuit device is a programmable integrated circuit device, said method further comprising:
generating a configuration bitstream based on said analyzing, said applying and said retiming; and
storing said configuration bitstream in memory of said programmable integrated circuit device.
3. The method of claim 1 wherein said analyzing is performed iteratively.
4. The method of claim 3 wherein:
said analyzing comprises determining circuit characteristics selected from the group consisting of slack, cycle slack, slack ratio and cycle slack ratio; and
said circuit characteristics are updated during said iterative analyzing.
5. The method of claim 3 wherein said analyzing comprises sequential timing analysis.
6. The method of claim 5 wherein said analyzing further comprises identifying reference points for said sequential timing analysis.
7. The method of claim 6 wherein said identifying reference points comprises:
selecting reference points from nodes in said critical and near-critical cyclic logic paths; and
updating said reference points as new ones of said critical and near-critical cyclic logic paths are identified during an iteration.
8. The method of claim 3 wherein said analyzing comprises updating lengths of said critical and near-critical cycles during each iteration based on results of said applying in a previous iteration.
9. The method of claim 1 wherein said analyzing comprises blending slack information and cycle slack information.
10. The method of claim 9 wherein said slack information and cycle slack information comprise slack ratios and cycle slack ratios.
11. The method of claim 1 wherein said retiming is performed by adjusting register delay.
12. The method of claim 1 wherein said retiming is performed by adjusting register clock skew.
13. The method of claim 1 wherein said applying timing optimizations other than retiming to said critical and near-critical cyclic logic paths further comprises excluding application of timing optimizations other than retiming to logic paths other than said critical and near-critical cyclic logic paths.
14. A non-transitory machine readable storage medium encoded with instructions for performing a method of configuring an integrated circuit device with a user logic design, said instructions comprising:
instructions to analyze said user logic design to identify critical and near-critical cyclic logic paths within said user logic design;
instructions to apply timing optimizations other than retiming to said critical and near-critical cyclic logic paths; and
instructions to retime logic paths without retiming said critical and near-critical cyclic logic paths.
15. The non-transitory machine readable storage medium of claim 14 wherein said integrated circuit device is a programmable integrated circuit device, said instructions further comprising:
instructions to generate a configuration bitstream based on said analyzing, said applying and said retiming; and
instructions to store said configuration bitstream in memory of said programmable integrated circuit device.
16. The non-transitory machine readable storage medium of claim 14 wherein instructions to analyze comprise instructions to analyze iteratively.
17. The non-transitory machine readable storage medium of claim 16 wherein:
said instructions to analyze comprise instructions to determine circuit characteristics selected from the group consisting of slack, cycle slack, slack ratio and cycle slack ratio; said instructions further comprising:
instructions to update said circuit characteristics during said iterative analyzing.
18. The non-transitory machine readable storage medium of claim 16 wherein said instructions to analyze comprise instructions to perform sequential timing analysis.
19. The non-transitory machine readable storage medium of claim 18 wherein said instructions to analyze further comprise instructions to identify reference points for said sequential timing analysis.
20. The non-transitory machine readable storage medium of claim 19 wherein said instructions to identify reference points comprise:
instructions to select reference points from nodes in said critical and near-critical cyclic logic paths; and
instructions to update said reference points as new ones of said critical and near-critical cyclic logic paths are identified during an iteration.
21. The non-transitory machine readable storage medium of claim 16 wherein said instructions to analyze comprise instructions to update lengths of said critical and near-critical cycles during each iteration based on results of said applying in a previous iteration.
22. The non-transitory machine readable storage medium of claim 14 wherein said instructions to analyze comprise instructions to blend slack information and cycle slack information.
23. The non-transitory machine readable storage medium of claim 22 wherein said slack information and cycle slack information comprise slack ratios and cycle slack ratios.
24. The non-transitory machine readable storage medium of claim 14 wherein said instructions to retime comprise instructions to adjust register delay.
25. The non-transitory machine readable storage medium of claim 14 wherein said instructions to retime comprise instructions to adjust register clock skew.
26. The non-transitory machine readable storage medium of claim 14 wherein said instructions to apply timing optimizations other than retiming to said critical and near-critical cyclic logic paths further comprise instructions to exclude timing optimizations other than retiming from application to logic paths other than said critical and near-critical cyclic logic paths.