Crossbar Switch Circuits And Methods In Integrated Circuits

1 . A configurable integrated circuit comprising:

first logic circuits;

second logic circuits; and

a first crossbar switch circuit comprising first multiplexer circuits and first input busses coupled to the first multiplexer circuits, wherein first inputs of each of the first multiplexer circuits are coupled to each of the first input busses, wherein the configurable integrated circuit is configurable to provide first input signals generated by the first logic circuits to the first inputs of each of the first multiplexer circuits through the first input busses, and wherein the first multiplexer circuits are configurable to provide first values of the first input signals that are received through the first input busses to the second logic circuits.

2 . The configurable integrated circuit of claim 1 , wherein the first logic circuits comprise first lookup table circuits, wherein the second logic circuits comprise second lookup table circuits, and wherein the first multiplexer circuits are configurable to provide the first values of the first input signals received from the first lookup table circuits through the first input busses to the second lookup table circuits.

3 . The configurable integrated circuit of claim 1 , wherein the first logic circuits comprise first configurable memory circuits, wherein the second logic circuits comprise second configurable memory circuits, and wherein the first multiplexer circuits are configurable to provide the first values of the first input signals received from the first configurable memory circuits through the first input busses to the second configurable memory circuits.

4 . The configurable integrated circuit of claim 1 , wherein the first crossbar switch circuit further comprises selection modification circuits that are configurable to adjust first select signals to the first multiplexer circuits to cause the first multiplexer circuits to bypass a row or column of third logic circuits.

5 . The configurable integrated circuit of claim 4 , wherein each of the selection modification circuits comprises a comparator circuit that compares a second select signal to a number of the row or column of the third logic circuits to generate a comparison output and a second multiplexer circuit that causes one of the first select signals to equal the second select signal or an incremented signal based on the comparison output.

6 . The configurable integrated circuit of claim 1 further comprising:

a second crossbar switch circuit comprising second multiplexer circuits and second input busses coupled to the second multiplexer circuits, wherein second inputs of each of the second multiplexer circuits are coupled to each of the second input busses, wherein the configurable integrated circuit is configurable to provide second input signals generated by the second logic circuits to the second inputs of each of the second multiplexer circuits through the second input busses, and wherein the second multiplexer circuits are configurable to provide second values of the second input signals that are received through the second input busses to third logic circuits.

7 . The configurable integrated circuit of claim 1 , wherein the first crossbar switch circuit is configurable to implement a second multiplexer circuit and a third multiplexer circuit in a circuit design for the integrated circuit.

8 . The configurable integrated circuit of claim 1 further comprising:

third logic circuits that are configurable to be coupled together to form larger circuit structures, wherein the first crossbar switch circuit is configurable to route signals to or from the third logic circuits.

9 . The configurable integrated circuit of claim 1 , wherein the first input busses in the first crossbar switch circuit are hardwired couplings to the first inputs of each of the first multiplexer circuits that are non-configurable.

10 . A method for transmitting first signals between first logic circuits and second logic circuits in a configurable integrated circuit, the method comprising:

providing the first signals from the first logic circuits to first multiplexer circuits through input busses, wherein a crossbar switch circuit in the configurable integrated circuit comprises the first multiplexer circuits and the input busses, and wherein inputs of each of the first multiplexer circuits are coupled to each of the input busses; and

providing values of the first signals from the input busses through the first multiplexer circuits in the crossbar switch circuit to the second logic circuits.

11 . The method of claim 10 further comprising:

configuring the first multiplexer circuits to select the values of the first signals using select signals generated by selection modification circuits.

12 . The method of claim 10 , wherein providing the values of the first signals from the input busses through the first multiplexer circuits in the crossbar switch circuit to the second logic circuits further comprises providing the values of the first signals from the input busses through the first multiplexer circuits to configurable memory circuits or lookup table circuits in the second logic circuits.

13 . The method of claim 10 further comprising:

selecting an incremented value of a first select signal as a second select signal based on a comparison between the first select signal and a number of a row or column of third logic circuits in the configurable integrated circuit; and

configuring one of the first multiplexer circuits to select one of the values of the first signals using the second select signal to bypass the row or column of the third logic circuits.

14 . The method of claim 10 further comprising:

configuring the first multiplexer circuits to implement a second multiplexer circuit and a third multiplexer circuit in a circuit design for the configurable integrated circuit.

15 . The method of claim 10 , wherein the input busses in the crossbar switch circuit are hardwired couplings to the inputs of each of the first multiplexer circuits that are non-configurable, and wherein each of the first signals is provided through one of the input busses to one of the inputs of each of the first multiplexer circuits.

16 . A non-transitory computer readable storage medium comprising instructions stored thereon that, when executed by a configurable integrated circuit, cause the configurable integrated circuit to:

configure first logic circuits in the configurable integrated circuit to provide signals through input busses to inputs of multiplexer circuits in a crossbar switch circuit in the configurable integrated circuit, wherein the inputs of each of the multiplexer circuits are coupled to each of the input busses; and

configure the multiplexer circuits to provide values of the signals to second logic circuits in the configurable integrated circuit.

17 . The non-transitory computer readable storage medium of claim 16 , wherein the instructions further cause the configurable integrated circuit to:

configure first lookup table circuits in the first logic circuits to generate the signals; and

configure the multiplexer circuits to provide the values of the signals to second lookup table circuits in the second logic circuits.

18 . The non-transitory computer readable storage medium of claim 16 , wherein the instructions further cause the configurable integrated circuit to:

configure first configurable memory circuits in the first logic circuits to generate the signals; and

configure the multiplexer circuits to provide the values of the signals to second configurable memory circuits in the second logic circuits.

19 . The non-transitory computer readable storage medium of claim 16 , wherein the instructions further cause the configurable integrated circuit to:

configure the multiplexer circuits to provide the values of the signals to configurable memory circuits or lookup table circuits in the second logic circuits.

20 . The non-transitory computer readable storage medium of claim 16 , wherein the input busses in the crossbar switch circuit are hardwired couplings to the inputs of each of the multiplexer circuits that are non-configurable.