Apparatus and method for improved integration circuitry in decision feedback equalization
View Patent ↗An embodiment of the present invention implements a linear feedback shift register (LFSR) as a counting device for an integrator of a DFE circuit. In embodiments of the present invention, the particular count sequence need not be known, instead only boundary values need be known. For example, for a LFSR having a predetermined count sequence, a digital integrator controller need not know every value of the count sequence. Instead, the digital integrator controller detects predetermined boundary values such as a minimum or maximum count.
1. A decision feedback equalization circuit, comprising:
a linear feedback shift register configured to count through a predetermined sequence;
a digital integrator controller configured to detect a first predetermined boundary value from the linear feedback shift register, wherein the digital integrator is configured to output a first digital integrator control signal responsive to the detection of the first predetermined boundary value;
a digital integrator configured to terminate integration responsive to the first digital integrator control signal.
2. The circuit of claim 1 , wherein the linear feedback shift register is a pseudo random generator.
3. The circuit of claim 1 , wherein the linear feedback shift register comprises at least two latches.
4. The circuit of claim 1 , wherein the linear feedback shift register comprises at least one XOR circuit.
5. The circuit of claim 1 , wherein the linear feedback shift register is configured to count up through the predetermined sequence.
6. The circuit of claim 5 , wherein the first predetermined boundary value is a maximum count value.
7. The circuit of claim 1 , wherein the linear feedback shift register is configured to count down through the predetermined sequence.
8. The circuit of claim 7 , wherein the first predetermined boundary value is a minimum count value.
9. The circuit of claim 1 , wherein the linear feedback shift register is configured to receive a first seed value.
10. The circuit of claim 1 , wherein the linear feedback shift register is configured to receive a signal that inhibits counting by the linear feedback shift register.
11. A decision feedback equalization circuit, comprising:
a counter configured to increment through a pseudo-random sequence of binary values;
a digital integrator controller configured to detect a first predetermined boundary value from the counter, wherein the digital integrator is configured to output a first digital integrator control signal responsive to the detection of the first predetermined boundary value;
a digital integrator configured to terminate integration responsive to the first digital integrator control signal.
12. The circuit of claim 11 , wherein the counter is a pseudo random generator.
13. The circuit of claim 11 , wherein the counter comprises at least two latches.
14. The circuit of claim 11 , wherein the counter comprises at least one XOR circuit.
15. The circuit of claim 11 , wherein the counter is configured to count up through the predetermined sequence.
16. The circuit of claim 15 , wherein the first predetermined boundary value is a maximum count value.
17. The circuit of claim 11 , wherein the counter is configured to count down through the predetermined sequence.
18. The circuit of claim 17 , wherein the first predetermined boundary value is a minimum count value.
19. The circuit of claim 11 , wherein the counter is configured to receive a first seed value.
20. The circuit of claim 11 , wherein the counter is configured to receive a signal that inhibits counting by the linear feedback shift register.
21. A decision feedback equalization circuit, comprising:
a digital integrator controller configured to receive a pseudo-random sequence of binary values, wherein the digital integrator is configured to output a first digital integrator control signal responsive to detection of the first predetermined boundary value;
a digital integrator configured to terminate integration responsive to the first digital integrator control signal.
22. The circuit of claim 15 , wherein the first predetermined boundary value is a maximum count value.
23. The circuit of claim 17 , wherein the first predetermined boundary value is a minimum count value.
24. The circuit of claim 11 , wherein the digital integrator controller is configured to detect an initial count value of the pseudo-random sequence of binary values.