Decoupling capacitor circuitry

1. An integrated circuit comprising:

first and second terminals;

a semiconductor substrate;

a layer of insulator on the semiconductor substrate;

a conductor on the layer of insulator configured to serve as a first conductive structure for an integrated circuit capacitor, wherein the conductor is electrically coupled to the first terminal; and

at least one density compliance structure that is electrically coupled to the second terminal and that is configured to serve as a second conductive structure for the integrated circuit capacitor, wherein the density compliance structure comprises polysilicon and wherein the conductor comprises a polysilicon gate structure.

2. The integrated circuit capacitor defined in claim 1 further comprising:

source-drain regions in the semiconductor substrate adjacent to the polysilicon gate structure, wherein the source-drain regions are coupled to the second terminal.

3. The integrated circuit capacitor defined in claim 2 further comprising:

a doped well in the semiconductor substrate, wherein a portion of the doped well lies under the layer of insulator, and wherein the source-drain regions are formed in the doped well.

4. The integrated circuit capacitor defined in claim 3 , wherein the doped well comprises an n-well, and wherein the source-drain regions comprise n+ doped regions.

5. The integrated circuit capacitor defined in claim 3 , wherein the doped well comprises a p-well, and wherein the source-drain regions comprise p+ doped regions.

6. An integrated circuit comprising:

first and second terminals;

a semiconductor substrate;

a layer of insulator on the semiconductor substrate;

a conductor on the layer of insulator configured to serve as a first conductive structure for an integrated circuit capacitor, wherein the conductor is electrically coupled to the first terminal;

at least one density compliance structure that is electrically coupled to the second terminal and that is configured to serve as a second conductive structure for the integrated circuit capacitor; and

source-drain regions in the semiconductor substrate, wherein the source-drain regions are coupled to the second terminal.

7. The integrated circuit capacitor defined in claim 6 further comprising:

a metal structure that is electrically coupled to the second terminal, that has at least one finger coupled to the source-drain regions, and that has at least one finger coupled to the density compliance structure.

8. The integrated circuit capacitor defined in claim 6 , wherein the at least one density compliance structure comprises first and second density compliance structures, the integrated circuit capacitor further comprising:

a metal structure that is electrically coupled to the second terminal, that has a first finger coupled to one of the source-drain regions, that has a second finger coupled to the first density compliance structure, and that has a third finger coupled to the second density compliance structure.

9. The integrated circuit capacitor defined in claim 8 , wherein the first density compliance structure is interposed between the second density compliance structure and the source-drain region to which the first finger is coupled.

10. The integrated circuit capacitor defined in claim 6 , wherein the at least one density compliance structure comprises first and second density compliance structures, the integrated circuit capacitor further comprising:

a metal structure that is coupled to the second terminal, wherein the metal structure includes a path coupled to one of the source-drain regions and a metal plate portion that overlaps both the first and second density compliance structures, wherein the metal structure is electrically coupled to the first density compliance structure and the second density compliance structure, and wherein the first density compliance structure is interposed between the second density compliance structure and the source-drain region to which the metal structure is coupled.

11. An integrated circuit comprising:

a power supply line;

a semiconductor substrate;

a layer of insulator on the semiconductor substrate;

a conductor on the layer of insulator; and

at least one density compliance structure that is electrically coupled to the power supply line, wherein the density compliance structure and the conductor form a capacitive structure, wherein the conductor comprises a polysilicon gate.

12. The integrated circuit capacitor defined in claim 11 , wherein the at least one density compliance structure comprises pollysilicon.

13. The integrated circuit capacitor defined in claim 11 , further comprising:

shallow trench isolation structures formed in the semiconductor substrate, wherein the density compliance structure is disposed over the shallow trench isolation structures.

14. The integrated circuit capacitor defined in claim 11 , further comprising:

an additional power supply line, wherein the additional power supply line is coupled to the conductor.

15. A method of forming an integrated circuit, comprising:

forming a layer of insulator on a semiconductor substrate;

forming a first conductive structure for an integrated circuit capacitor by forming a gate structure on the layer of insulator;

forming first and second source-drain regions in the semiconductor substrate adjacent to the gate structure;

forming a second conductive structure for the integrated circuit capacitor by forming at least one density compliance structure on the semiconductor substrate; and

coupling the density compliance structure to the first source-drain region to increase the capacitance of the integrated circuit capacitor.

16. The method defined in claim 15 , further comprising:

coupling a power supply line to the at least one density-compliance structure.

17. The method defined in claim 15 , further comprising:

coupling the gate structure to a power supply path.

18. The method defined in claim 15 , further comprising:

shorting the first source-drain region and the second source-drain region.