Integrated circuit device with embedded programmable logic
View Patent ↗Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.
1. A system comprising:
a first integrated circuit; and
a second integrated circuit communicatively coupled to the first integrated circuit, wherein the second integrated circuit comprises:
a primary circuitry; and
an embedded programmable logic, wherein the embedded programmable logic is embedded in an interposer configured to facilitate communication between the first integrated circuit and the second integrated circuit, embedded in the second integrated circuit, or embedded in both the interposer and the second integrated circuit;
wherein the first integrated circuit and the second integrated circuit are configured to complement the operation of the other, and wherein the first integrated circuit is configured to adjust the functionality of the primary circuitry of the second integrated circuit by programming the embedded programmable logic.
2. The system of claim 1 , wherein the primary circuitry comprises a memory module and the embedded programmable logic is configured to be programmed to an implement a data or address function, wherein the data or address function comprises incrementing a memory address, decrementing a memory address, configuring a memory port, configuring a memory mode, or any combination thereof.
3. The system of claim 1 , wherein the primary circuitry comprises a memory module and the embedded programmable logic is configured to be programmed to implement a configuration or testing function, wherein the testing or configuration function comprises a built-in self-test, debugging, a performance characterization, controlling the memory, or any combination thereof.
4. The system of claim 1 , wherein the primary circuitry comprises a memory module and the embedded programmable logic is configured to be programmed to implement a computational function, wherein the computational function comprises pattern matching, determining statistics, or any combination thereof.
5. The system of claim 1 , wherein the primary circuitry comprises an application-specific integrated circuit and the embedded programmable logic is configured to be programmed to implement a computational function, wherein the computational function comprises synchronizing communication, facilitating handshaking, interface protocol conversion, throughput matching, or any combination thereof.
6. The system of claim 1 , wherein the primary circuitry comprises a transceiver and the embedded programmable logic is configured to be programmed to implement a computational function, wherein the computational function comprises interface protocol conversion, encryption, decryption, encoding, decoding, error correction, signal conditioning, signal detection, or any combination thereof.
7. The system of claim 1 , wherein the primary circuitry comprises a transceiver and the embedded programmable logic is configured to be programmed to implement a configuration or testing function, wherein the testing function comprises testing the transceiver, maintaining the transceiver, or any combination thereof.
8. The system of claim 1 , wherein the primary circuitry comprises a system on a chip and the embedded programmable logic is configured to be programmed to implement a computational function, wherein the computational function comprises interface protocol conversion, memory mode conversion, or any combination thereof.
9. The system of claim 1 , wherein the embedded programmable logic is configured to enable a first portion of the embedded programmable logic to be programmed while a second portion of the embedded programmable logic remains substantially the same.
10. The system of claim 1 , wherein the embedded programmable logic is configured to be programmed through configuration memory, metal programmable logic, or any combination thereof.
11. The system of claim 1 , wherein the embedded programmable logic is configured to be statically programmed.
12. The system of claim 1 , wherein the embedded programmable logic is configured to be dynamically programmed.
13. A method for adjusting the functionality of a primary circuitry of an integrated circuit, comprising:
receiving a configuration signal from another integrated circuit, a separate computing device, or both;
programming a function on an embedded programmable logic in the integrated circuit, wherein the function is based at least in part on the configuration signal, and configured to adjust the functionality of the primary circuitry of the integrated circuit; and
performing the function on the embedded programmable logic.
14. The method of claim 13 , wherein the primary circuitry of the integrated circuit comprises a memory module and the function comprises a data or address function, wherein the data or address function comprises incrementing a memory address, decrementing a memory address, caching data, configuring a memory port, configuring a memory mode, controlling the memory, or any combination thereof.
15. The method of claim 13 , wherein the primary circuitry of the integrated circuit comprises a memory module and the function comprises a computational function, wherein the computational function comprises pattern matching, determining statistics, or any combination thereof.
16. The method of claim 13 , wherein the primary circuitry of the integrated circuit comprises a memory module and the function comprises a testing function, wherein the testing function comprises a built-in self-test, debugging, a performance characterization, or any combination thereof.
17. The method of claim 13 , wherein the primary circuitry of the integrated circuit comprises an application-specific integrated circuit and the function comprises an interfacing function, wherein the interfacing function comprising synchronizing communication, facilitating handshaking, interface protocol conversion, throughput matching, or any combination thereof.
18. The method of claim 13 , wherein the primary circuitry of the integrated circuit comprises a transceiver and the function comprises an interfacing function, wherein the interfacing function comprises serial protocol conversion, encryption, decryption, encoding, decoding, error correction, signal conditioning, signal detection, or any combination thereof.
19. The method of claim 13 , wherein the primary circuitry of the integrated circuit comprises a system on a chip and the function includes an interfacing function, wherein the interfacing function comprises interface protocol conversion, memory mode conversion, or any combination thereof.
20. A system comprising:
a first integrated circuit configured to generate a configuration signal; and
a peripheral integrated circuit programmed to support the functionality of the first integrated circuit, wherein the peripheral integrated circuit comprises:
a configuration signal port configured to receive the configuration signal; and
an embedded programmable logic communicatively coupled to the configuration signal port, wherein the programmable logic is configured to be programmed based at least in part on the configuration signal;
wherein the configuration signal includes instructions for programming the embedded programmable logic with a function for supporting the functionality of the primary integrated circuit.