Systems And Methods For Generating Redacted Circuit Designs For Integrated Circuits
A computer system is provided for protecting an original circuit design for an integrated circuit. The computer system includes a logic circuit replacement tool that generates a redacted circuit design for the integrated circuit by replacing logic circuits in the original circuit design with first and second configurable circuits that perform logic functions of the logic circuits when a bitstream stored in storage circuits configures the first and the second configurable circuits. The logic circuit replacement tool couples one of the storage circuits that stores a bit in the bitstream to an input in each of the first and the second configurable circuits in the redacted circuit design.
1 . A computer system for protecting an original circuit design for an integrated circuit, the computer system comprising:
a logic circuit replacement tool for generating a redacted circuit design for the integrated circuit by replacing logic circuits in the original circuit design with configurable circuits that perform logic functions of the logic circuits when a bitstream stored in storage circuits configures the configurable circuits,
wherein the logic circuit replacement tool causes the redacted circuit design to share a first bit in the bitstream between at least two of the configurable circuits by coupling a first one of the storage circuits that stores the first bit to a first input of each of the at least two of the configurable circuits.
2 . The computer system of claim 1 , wherein each of the at least two of the configurable circuits comprises a lookup table circuit, and wherein the first one of the storage circuits is coupled to a data input of a multiplexer circuit in the lookup table circuit in each of the at least two of the configurable circuits.
3 . The computer system of claim 1 , wherein the logic circuit replacement tool causes the redacted circuit design to share a second bit in the bitstream between the at least two of the configurable circuits by coupling a second one of the storage circuits that stores the second bit to a second input of each of the at least two of the configurable circuits.
4 . The computer system of claim 1 , wherein the logic circuit replacement tool refrains from replacing any of the logic circuits in the original circuit design with a lookup table circuit that only consists of a single select input.
5 . The computer system of claim 1 , wherein the logic circuit replacement tool refrains from replacing any of the logic circuits in the original circuit design with an additional configurable circuit having at least two inputs that are coupled to one of the storage circuits that stores a single bit in the bitstream.
6 . The computer system of claim 1 , wherein the logic circuit replacement tool refrains from replacing any of the logic circuits in the original circuit design with an additional configurable circuit that receives a reset signal at an input.
7 . The computer system of claim 1 , wherein the logic circuit replacement tool is configured to replace at least one of the logic circuits in the original circuit design with a lookup table circuit comprising at least three select inputs.
8 . The computer system of claim 1 , wherein the logic circuit replacement tool refrains from replacing any of the logic circuits in the original circuit design with an additional configurable circuit that receives bits in the bitstream in a first order and another configurable circuit that receives the bits in the bitstream in a second order that is permutated with respect to the first order.
9 . A method for redacting an original circuit design for an application specific integrated circuit to generate a redacted circuit design, the method comprising:
replacing logic circuits in the original circuit design with configurable circuits in the redacted circuit design that perform logic functions of the logic circuits when a bitstream stored in storage circuits configures the configurable circuits; and
sharing a first bit in the bitstream between at least two of the configurable circuits in the redacted circuit design to cause the first bit in the bitstream to configure the at least two of the configurable circuits.
10 . The method of claim 9 further comprising:
sharing a second bit in the bitstream between the at least two of the configurable circuits in the redacted circuit design to cause the second bit in the bitstream to configure the at least two of the configurable circuits.
11 . The method of claim 9 , wherein replacing the logic circuits in the original circuit design with the configurable circuits further comprises:
refraining from replacing any of the logic circuits in the original circuit design with an additional configurable circuit that only consists of a single select input.
12 . The method of claim 9 , wherein replacing the logic circuits in the original circuit design with the configurable circuits further comprises:
refraining from replacing any of the logic circuits in the original circuit design with an additional configurable circuit having at least two inputs that receive a same configuration bit in the bitstream.
13 . The method of claim 9 , wherein replacing the logic circuits in the original circuit design with the configurable circuits further comprises:
refraining from replacing any of the logic circuits in the original circuit design with an additional configurable circuit that receives a reset signal at an input.
14 . The method of claim 9 , wherein replacing the logic circuits in the original circuit design with the configurable circuits further comprises:
replacing at least one of the logic circuits in the original circuit design with one of the configurable circuits that comprises at least three select inputs.
15 . The method of claim 9 , wherein replacing the logic circuits in the original circuit design with the configurable circuits further comprises:
refraining from replacing the logic circuits in the original circuit design with an additional configurable circuit that receives configuration bits in the bitstream in a first order and another configurable circuit that receives the configuration bits in the bitstream in a second order that is different than the first order.
16 . A non-transitory computer readable storage medium comprising instructions stored thereon for causing a computing system to execute a method for redacting an original circuit design for an application specific integrated circuit, the method comprising:
generating options of different configurable circuits for replacing a logic circuit in the original circuit design; and
selecting one of the different configurable circuits to replace the logic circuit in a redacted circuit design for the application specific integrated circuit, wherein one of the generating or the selecting is performed using a random number.
17 . The non-transitory computer readable storage medium of claim 16 , wherein the method further comprises:
generating the random number using key based variation.
18 . The non-transitory computer readable storage medium of claim 16 , wherein the random number is generated by a pseudo random number generator.
19 . The non-transitory computer readable storage medium of claim 16 , wherein generating the options of the different configurable circuits for replacing the logic circuit comprises generating at least one of the different configurable circuits with an additional logic circuit and a multiplexer circuit that is configured to bypass the additional logic circuit.
20 . The non-transitory computer readable storage medium of claim 16 , wherein generating the options of the different configurable circuits for replacing the logic circuit comprises generating at least one of the different configurable circuits with circuitry that is unused in the redacted circuit design.