Method and apparatus for performing multiple stage physical synthesis

1. A method for designing a system on a target device, the method comprising:

mapping a system on the target device;

placing the system on the target device; and

performing physical synthesis on the system subsequent to the mapping procedure and prior to the placing procedure by performing circuit transformations on a circuit in the system to reduce an area required for implementing the circuit, wherein at least one of the mapping, placing, and performing is performed by a processor.

2. The method of claim 1 , wherein the circuit transformations on the circuit allows the system to satisfy a timing constraint.

3. The method of claim 1 , wherein the circuit transformations on the circuit reduces power consumption.

4. The method of claim 1 further comprising:

routing the system; and

performing a second physical synthesis on the system, which experienced the first physical synthesis, after the routing.

5. The method of claim 4 , wherein performing the second physical synthesis comprises performing circuit transformation on a circuit to improve an existing routing of the system.

6. The method of claim 1 further comprising legalizing the circuit transformations.

7. The method of claim 6 , wherein legalizing the circuit transformations comprises performing incremental placement.

8. The method of claim 6 , wherein legalizing the circuit transformations comprises performing one of rotation, decomposition and inversion to re-implement a look-up-table.

9. The method of claim 6 , wherein legalizing the circuit transformation comprises performing incremental routing.

10. A method for designing a system on a target device, the method comprising:

mapping a system on the target device;

placing the system on the target device; and

performing physical synthesis on the system subsequent to the mapping procedure and prior to the placing procedure by performing circuit transformations on a circuit in the system to reduce power consumption of the circuit, wherein at least one of the mapping, placing, and performing is performed by a processor.

11. The method of claim 10 , wherein the circuit transformations on the circuit allows the system to satisfy a timing constraint.

12. The method of claim 10 , wherein the circuit transformations on the circuit reduces an area required for implementing the circuit.

13. The method of claim 10 further comprising:

routing the system; and

performing a second physical synthesis on the system, which experienced the first physical synthesis, after the routing.

14. The method of claim 13 , wherein performing the second physical synthesis comprises performing circuit transformation on a circuit to improve an existing routing of the system.

15. The method of claim 10 further comprising legalizing the circuit transformations.

16. The method of claim 15 , wherein legalizing the circuit transformations comprises performing incremental placement.

17. The method of claim 15 , wherein legalizing the circuit transformations comprises performing one of rotation, decomposition and inversion to re-implement a look-up-table.

18. The method of claim 15 , wherein legalizing the circuit transformation comprises performing incremental routing.

19. A system designer comprising:

a synthesis unit that generates a design for a system;

a mapping unit that determines available components on a target device to implement the design;

a placement unit that assigns components on the target device to the system;

a physical synthesis unit that performs physical synthesis on the system subsequent to the determining performed by the mapping unit and prior to the placement unit assigning the components on the target device to the system, wherein the physical synthesis involves performing circuit transformations on a circuit in the system to reduce an area required for implementing the circuit, and wherein at least one of the synthesis unit, mapping unit, placement unit, and physical synthesis unit is implemented by hardware.

20. The system designer of claim 19 , wherein the physical synthesis unit comprises:

an estimator unit operable to estimate characteristics of the circuit in the design;

an optimization unit operable to perform the circuit transformations on the circuit in the system; and

a legalization unit operable to legalize the circuit transformations.

21. The system designer of claim 20 , wherein the circuit transformations on the circuit allows the system to satisfy a timing constraint.