FPGA configuration data scrambling using input multiplexers
View Patent ↗Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.
1. A method of configuring a configurable integrated circuit comprising:
retrieving a key from a first memory in the integrated circuit;
receiving configuration data at an input port to the integrated circuit; and
descrambling the configuration data by multiplexing the configuration data,
wherein the configuration data is multiplexed under control of the key retrieved from the memory.
2. The method of claim 1 wherein the configuration data is descrambled by multiplexing the configuration data such that bits of the configuration data are reordered.
3. The method of claim 1 further comprising:
storing the multiplexed configuration data in a second memory; and
configuring the configurable integrated circuit using the multiplexed configuration data in the second memory.
4. The method of claim 3 further comprising:
before retrieving the key from the first memory, receiving key information at the input port to the configurable integrated circuit; and
storing the key in the first memory.
5. The method of claim 1 wherein the first memory is a nonvolatile memory.
6. The method of claim 5 wherein the first memory is a fuse array.
7. The method of claim 1 wherein the input port to the configurable integrated circuit is a JTAG port.
8. The method of claim 1 wherein the configurable integrated circuit is a field-programmable gate array.