2.5D electronic package
View Patent ↗A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.
1. A method comprising:
providing a package substrate having first and second major surfaces;
providing an integrated circuit having first and second major surfaces with a plurality of active devices in the integrated circuit, wherein the integrated circuit is mounted so that the first major surface of the integrated circuit faces the package substrate, wherein a plurality of interconnection layers and intermetallic dielectric layers are in the integrated circuit, and wherein an uppermost interconnect layer of the plurality of interconnection layers has a thickness no greater than that of any other one of the plurality of interconnection layers; and
providing an interposer between the integrated circuit and the package substrate with the integrated circuit mounted on the interposer, the interposer having at least one interconnection layer that is used primarily for power distribution in the integrated circuit, wherein the at least one interconnection layer in the interposer that is used primarily for power distribution in the integrated circuit extends across an entire width of the interposer.
2. The method of claim 1 , wherein the interposer comprises a semiconductor material having first and second major surfaces and a plurality of conducting vias extending between the first and second major surfaces of the interposer.
3. The method of claim 2 , wherein the plurality of interconnection layers in the integrated circuit are vertically stacked.
4. The method of claim 1 , wherein the integrated circuit is made of silicon, and wherein the interposer is a thin layer of silicon having first and second major surfaces and a plurality of through-silicon-vias that provide conductive paths between the first and second major surfaces of the interposer.
5. The method of claim 4 , wherein the interposer has a thickness that is about 100 microns or less, and the through-silicon-vias have a diameter that is about 10 microns or less.
6. The method of claim 1 , wherein the integrated circuit is mounted on the interposer in flip-chip fashion.
7. The method of claim 1 , wherein the interposer is a thin, flat substrate having first and second major surfaces with interconnection layers on both major surfaces.
8. A method comprising:
providing a package substrate having first and second major surfaces;
providing an integrated circuit having first and second major surfaces with a plurality of active devices in the integrated circuit, wherein the integrated circuit is mounted so that the first major surface of the integrated circuit faces the package substrate, wherein a plurality of interconnection layers and intermetallic dielectric layers are in the integrated circuit, and wherein an uppermost interconnect layer of the plurality of interconnection layers has a thickness no greater than that of any other one of the plurality of interconnection layers; and
providing an interposer between the integrated circuit and the package substrate with the integrated circuit mounted on the interposer, the interposer having at least one interconnection layer that is used primarily for power distribution in the integrated circuit, wherein the at least one interconnection layer in the interposer that is used primarily for power distribution in the integrated circuit is at least as wide as the integrated circuit.
9. The method of claim 8 , wherein the interposer comprises a semiconductor material having first and second major surfaces and a plurality of conducting vias extending between the first and second major surfaces of the interposer.
10. The method of claim 9 , wherein the plurality of interconnection layers in the integrated circuit are vertically stacked.
11. The method of claim 8 , wherein the integrated circuit is made of silicon, and wherein the interposer is a thin layer of silicon having first and second major surfaces and a plurality of through-silicon-vias that provide conductive paths between the first and second major surfaces of the interposer.
12. The method of claim 11 , wherein the interposer has a thickness that is about 100 microns or less and the through-silicon-vias have a diameter that is about 10 microns or less.
13. The method of claim 8 , wherein the integrated circuit is mounted on the interposer in flip-chip fashion.
14. The method of claim 8 , wherein the interposer is a thin, flat substrate having first and second major surfaces with interconnection layers on both major surfaces.