Partial reconfiguration and error detection in an integrated circuit

1. A method of partially configuring an IC, comprising:

receiving an error checking value and a partial reconfiguration data, wherein at least a portion of bits in the partial reconfiguration data is similar to a prior configuration data stored in the IC;

performing a first logic operation on the partial reconfiguration data and the prior configuration data to generate an updated configuration data;

performing a second logic operation on the prior configuration data, the partial reconfiguration data and the updated configuration data to generate a temporary configuration data;

calculating a temporary error checking value for the temporary configuration data;

performing a third logic operation on the error checking value, the temporary error checking value and a prior error checking value stored in the IC to generate an updated error checking value for the updated configuration data; and

storing the updated error checking value in the IC, wherein the updated error checking value replaces the prior error checking value.

2. The method of claim 1 , wherein the error checking value is calculated based solely on the partial reconfiguration data.

3. The method of claim 1 , wherein the first logic operation includes OR-ing the partial reconfiguration data and the prior configuration data, the second logic operation includes XOR-ing the prior configuration data, the partial reconfiguration data and the updated configuration data, and wherein the third logic operation includes XOR-ing the error checking value, the temporary error checking value and the prior error checking value.

4. The method of claim 1 , further comprising:

storing the updated configuration data in the IC, wherein the updated configuration data replaces the prior configuration data in the IC.

5. The method of claim 1 , wherein the error checking value is a cyclic redundancy check (CRC) value calculated based solely on the partial reconfiguration data.

6. The method of claim 5 , wherein the CRC value is pre-calculated with an electronic design automation (EDA) tool.

7. The method of claim 5 , wherein the CRC value is calculated based on one of an entire bitstream of the partial reconfiguration data or each frame of the entire bitstream of the partial reconfiguration data.

8. An integrated circuit (IC), comprising:

a first logical operator circuit coupled to receive a partial reconfiguration data;

a storage unit having a prior configuration data coupled to the first logical operator circuit, wherein the first logical operator circuit outputs an updated configuration data based on a combination of the partial reconfiguration data and the prior configuration data;

a second logical operator circuit coupled to receive the updated configuration data from the first logical operator circuit, wherein the second logical operator circuit outputs a temporary configuration data based on the updated configuration data, the prior configuration data and the partial reconfiguration data;

a cyclic redundancy check (CRC) generator circuit coupled to the second logical operator circuit; and

a third logical operator circuit coupled to receive a CRC value based on the partial reconfiguration data and an output from the CRC generator circuit, wherein the third logical operator circuit generates an updated CRC value based on the CRC value, the output from the CRC generator circuit and a prior CRC value stored in the IC.

9. The circuit of claim 8 , wherein the first logical operator circuit includes an OR gate, and wherein the second and third logical operator circuits each includes an XOR gate.

10. The circuit of claim 8 , further comprising:

an error detection circuit, wherein the error detection circuit compares the updated configuration data with the updated CRC value.

11. The circuit of claim 8 , further comprising:

another storage unit holding the prior CRC value coupled to the third logical operator circuit.

12. The circuit of claim 8 , wherein the storage unit coupled to the first logical operator circuit includes a CRAM array and wherein the CRAM array is updated with the updated configuration data from the second logical operator circuit.

13. The circuit of claim 8 , wherein the partial reconfiguration data and the CRC value based on the partial reconfiguration data are received from a source external to the IC.