Metastability-hardened synchronization circuit
View Patent ↗An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.
1. An integrated circuit (IC), comprising:
a metastability-hardened synchronization circuit, comprising:
a plurality of sampling circuits that sample an input signal to generate a plurality of sampled signals; and
a multiplexer that generates an output signal from the plurality of sampled signals by using a clock signal as a select signal, the clock signal having a frequency selected to reduce metastability of the synchronization circuit.
2. The integrated circuit (IC) according to claim 1 , wherein each sampling circuit in the plurality of sampling circuits comprises a plurality of storage circuits coupled in a cascade arrangement.
3. The integrated circuit (IC) according to claim 2 , wherein the plurality of storage circuits in each sampling circuit comprises flip-flops.
4. The integrated circuit (IC) according to claim 1 , wherein each sampling circuit in the plurality of sampling circuits is clocked by a respective phase of the clock signal.
5. The integrated circuit (IC) according to claim 4 , wherein the metastability-hardened synchronization circuit comprises first and second sampling circuits.
6. The integrated circuit (IC) according to claim 5 , wherein each of the first and second sampling circuits comprises a pair of flip-flops coupled in a cascade arrangement.
7. The integrated circuit (IC) according to claim 5 , wherein the first sampling circuit is clocked by the clock signal, and the second sampling circuit is clocked by a complement of the clock signal.
8. The integrated circuit (IC) according to claim 1 , wherein the input signal comprises an asynchronous signal.
9. The integrated circuit (IC) according to claim 8 , wherein the output signal comprises a synchronous signal.
10. The integrated circuit (IC) according to claim 1 , further comprising programmable logic circuitry, wherein the metastability-hardened synchronization circuit is included in the programmable logic circuitry.
11. The integrated circuit (IC) according to claim 1 , further comprising programmable interconnect circuitry, wherein the metastability-hardened synchronization circuit is included in the programmable interconnect circuitry.
12. A method of processing signals by using a metastability-hardened synchronization circuit, the method comprising:
sampling an input signal with a plurality of sampling circuits to generate a plurality of sampled signals; and
multiplexing the plurality of sampled signals to generate an output signal from the plurality of sampled signals by using a clock signal as a select signal, the clock signal having a frequency selected to reduce metastability of the synchronization circuit.
13. The method according to claim 12 , wherein sampling the input signal with a plurality of sampling circuits comprises sampling the input signal with a plurality of storage circuits coupled in a cascade arrangement.
14. The method according to claim 13 , wherein the plurality of storage circuits in each sampling circuit comprises flip-flops.
15. The method according to claim 12 , further comprising clocking each sampling circuit in the plurality of sampling circuits by a respective phase of the clock signal.
16. The method according to claim 15 , wherein the metastability-hardened synchronization circuit comprises first and second sampling circuits.
17. The method according to claim 16 , wherein each of the first and second sampling circuits comprises a pair of flip-flops coupled in a cascade arrangement.
18. The method according to claim 16 , further comprising:
clocking the first sampling circuit by the clock signal; and
clocking the second sampling circuit by a complement of the clock signal.
19. The method according to claim 12 , wherein the input signal comprises an asynchronous signal.
20. The method according to claim 19 , wherein the output signal comprises a synchronous signal.
21. The method according to claim 12 , wherein the metastability-hardened synchronization circuit is included in programmable logic circuitry.
22. The method according to claim 12 , wherein the metastability-hardened synchronization circuit is included in programmable interconnect circuitry.