Mixed-Radix Multiplier Circuit
Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include input circuitry, mixed-radix partial product generation circuitry, and partial product addition circuitry. The input circuitry may receive the multiplicand value and the multiplier value. The mixed-radix partial product generation circuitry may generate partial products that include a first radix partial product according to a first radix coding and a second radix partial product according to a second radix coding. The partial product addition circuitry may add the partial products to generate a product of the multiplicand value and multiplier value.
1 . Multiplier circuitry to multiply a multiplicand value with a multiplier value, the multiplier circuitry comprising:
input circuitry to receive the multiplicand value and the multiplier value; and
mixed-radix partial product generation circuitry to generate partial products that include a first radix partial product according to a first radix coding and a second radix partial product according to a second radix coding; and
partial product addition circuitry to add the partial products to generate a product of the multiplicand value and multiplier value.
2 . The multiplier circuitry of claim 1 , wherein the mixed-radix partial product generation circuitry comprises partial product coding circuitry to encode a first set of bits of the multiplier value according to the first radix coding and encode a second set of bits of the multiplier value according to the second radix coding.
3 . The multiplier circuitry of claim 2 , wherein the first radix coding comprises a radix 8 encoding and the second radix coding comprises a radix 4 encoding.
4 . The multiplier circuitry of claim 2 , wherein the first radix coding comprises a form of Booth's radix 8 encoding.
5 . The multiplier circuitry of claim 2 , wherein the second radix coding comprises a form of Booth's radix 4 encoding.
6 . The multiplier circuitry of claim 1 , wherein the partial product addition circuitry comprises a number of levels less than or equal to a minimum depth to reduce partial products that would be produced by first radix single-radix partial product generation circuitry on other multiplicand values and other multiplier values of the same bit depth as the multiplicand value and the multiplier value using only the first radix coding.
7 . The multiplier circuitry of claim 6 , wherein the number of levels is less than or equal to a minimum depth to reduce partial products that would be produced by second radix single-radix partial product generation circuitry on other multiplicand values and other multiplier values of the same bit depth as the multiplicand value and the multiplier value using only the second radix coding.
8 . The multiplier circuitry of claim 1 , wherein the multiplier circuitry is decomposed into at least two smaller multiplier circuits, wherein a first of the at least two smaller multiplier circuits comprises a first portion of the mixed-radix partial product generation circuitry and a first portion of the partial product addition circuitry and a second of the at least two smaller multiplier circuits comprises a second portion of the mixed-radix partial product generation circuitry and a second portion of the partial product addition circuitry.
9 . The multiplier circuitry of claim 1 , wherein the partial product addition circuitry is to reduce the partial products in an order different from least significant to most significant.
10 . The multiplier circuitry of claim 1 , wherein the partial product addition circuitry is to reduce a first set of the partial products while a second set of the partial products are still being generated.
11 . An article of manufacture comprising one or more tangible, non-transitory, machine-readable media comprising instructions that, when executed by a data processing system, result in operations comprising:
generating a set of possible multiplier designs that comprises at least one mixed-radix multiplier design;
selecting a multiplier design from among the set of possible multiplier designs; and
generating a circuit design that includes the selected multiplier design.
12 . The article of manufacture of claim 11 , wherein generating the set of possible multiplier designs comprises generating multiple multiplier designs having different respective partial product coding circuitry designs.
13 . The article of manufacture of claim 11 , wherein generating the set of possible multiplier designs comprises generating multiple multiplier designs having different respective partial product addition circuitry designs.
14 . The article of manufacture of claim 13 , wherein generating the set of possible multiplier designs comprises generating multiple multiplier designs having a common mixed-radix partial product coding circuitry designs but different respective partial product addition circuitry designs.
15 . The article of manufacture of claim 11 , wherein the instructions result in operations comprising calculating a cost function value for respective multiplier designs of the multiplier designs and wherein selecting the multiplier design from among the set of possible multiplier designs comprises selecting the multiplier design with the lowest cost function value.
16 . The article of manufacture of claim 15 , wherein the cost function considers area or speed, or both area and speed.
17 . An integrated circuit comprising:
mixed-radix partial product coding circuitry to generate partial product codes according to a plurality of radix coding schemes as applied to bits of a multiplier value;
partial product multiplexers to select a multiple of a multiplicand value based on the partial product codes to generate a set of partial products; and
partial product addition circuitry to add the set of partial products to generate a product of the multiplicand value and multiplier value.
18 . The integrated circuit of claim 17 , wherein the mixed-radix partial product coding circuitry is to generate a first partial product code for a first set of the bits of the multiplier value according to a first radix coding scheme of the plurality of radix coding schemes and to generate a second partial product code for a second set of the bits of the multiplier value according to a second radix coding scheme of the plurality of radix coding schemes, wherein the first set of bits is of a different number than the second set of bits.
19 . The integrated circuit of claim 17 , wherein the partial product addition circuitry comprises a compression tree composed of compressors no larger than 3-2 compressors.
20 . The integrated circuit of claim 17 , wherein the integrated circuit comprises a processor, an application specific integrated circuit (ASIC), or a programmable logic device, or any combination thereof.