Multi-level signaling for on-package chip-to-chip interconnect through silicon bridge

1. An apparatus for data communication between at least two in-package semiconductor dies, the apparatus comprising:

an digital-to-analog converter on a first semiconductor die in a package that converts a plurality of binary signals to an analog signal and drives the analog signal; and

a silicon bridge for receiving the analog signal from the first semiconductor die and transmitting the analog signal to a second semiconductor die in the package; and

an analog-to-digital converter on the second semiconductor die that receives the analog signal from the silicon bridge and converts the analog signal to a plurality of recovered binary signals.

2. The apparatus of claim 1 , wherein the plurality of binary signals comprises n binary signals, where n is an integer that is two or more, and wherein the digital-to-analog converter comprises an N-level digital-to-analog converter, where N=2 n .

3. The apparatus of claim 1 , further comprising:

a first register on the first semiconductor die that receives a multiple-bit data signal from logic circuitry on the first semiconductor die and outputs the plurality of binary signals to the digital-to-analog converter.

4. The apparatus of claim 1 , further comprising:

a first register on the first semiconductor die that receives a multiple-bit data signal from logic circuitry on the first semiconductor die and outputs the plurality of binary signals to the digital-to-analog converter; and

a second register on the second semiconductor die that receives the plurality of recovered binary signals from the analog-to-digital converter and outputs an multiple-bit recovered data signal to logic circuitry on the second semiconductor die.

5. The apparatus of claim 4 , further comprising:

a clock transmitter on the first semiconductor die that transmits a clock signal through the silicon bridge to the second semiconductor die; and

a clock receiver on the second semiconductor die that receives the clock signal.

6. The apparatus of claim 5 , wherein the clock signal is provided to the first register and provides timing for switching the binary signals.

7. The apparatus of claim 6 , further comprising:

an inverter on the second semiconductor die that receives the clock signal and outputs an inverted clock signal,

wherein the inverted clock signal is provided to the analog-to-digital converter and provides timing for sampling the analog signal.

8. A method of data communication between at least two in-package semiconductor dies, the method comprising:

receiving by a first register a multiple-bit data signal from logic circuitry on a first semiconductor die;

outputting the plurality of binary signals to a digital-to-analog converter;

converting a plurality of binary signals to an analog signal by the digital-to-analog converter on the first semiconductor die in a package;

transmitting the analog signal through a silicon bridge to a second semiconductor die in the package;

converting the analog signal to a plurality of recovered binary signals by an analog-to-digital converter on the second semiconductor die;

receiving by a second register the plurality of recovered binary signals from the analog-to-digital converter; and

outputting an multiple-bit recovered data signal to logic circuitry on the second semiconductor die.

9. The method of claim 8 , wherein the plurality of binary signals comprises n binary signals, where n is an integer that is two or more, and wherein the digital-to-analog converter comprises an N-level digital-to-analog converter, where N=2 n .

10. The method of claim 8 , further comprising:

transmitting a clock signal through the silicon bridge to the second semiconductor die by a clock transmitter on the first semiconductor die; and

receiving the clock signal by a clock receiver on the second semiconductor die.

11. The method of claim 10 , wherein the clock signal is provided to the first register and provides timing for switching the binary signals.

12. The method of claim 11 , further comprising:

receiving the clock signal and outputting an inverted clock signal by an inverter on the second semiconductor die; and

using the inverted clock signal by the second register to provide timing for sampling of the analog signal.

13. An apparatus for data communication between at least two in-package semiconductor dies, the apparatus comprising:

a first digital-to-analog converter on a first semiconductor die in a package that converts a first plurality of binary signals to a first analog signal and drives the first analog signal to a silicon bridge;

a first analog-to-digital converter on the first semiconductor die that receives a second analog signal from the silicon bridge and converts the second analog signal to a first plurality of recovered binary signals;

a second digital-to-analog converter on a second semiconductor die in the package that converts a second plurality of binary signals to the second analog signal and drives the second analog signal to the silicon bridge; and

a second analog-to-digital converter on the second semiconductor die that receives the first analog signal from the silicon bridge and converts the first analog signal to a second plurality of recovered binary signals.